Laterally diffused MOS transistor having N+ source contact to N-doped substrate

Abstract

Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.

1. A LDMOS transistor comprising:
 a) aan N-doped substrate,; 
 b) a P-doped epitaxial layer on the N-doped substrate with a P+ doped buried layer in the epitaxial layer,; 
 c) a gate electrode on a dielectric layer on the surface of the P-doped epitaxial layer and over a P-doped channel region in the P-doped epitaxial layer,; 
 d) aan N-doped drain region in the P-doped epitaxial layer extending from one side of the gate electrode,; 
 e) aan N-doped source region in the P-doped epitaxial layer extending from an opposing side of the gate electrode,; and 
 f) a source contact extending through the P-doped epitaxial layer and the P+ buried layer into the N-doped substrate and connecting the N-doped source region to the N-doped substrate. 
 
     
     
       2. The LDMOS transistor as defined by of  claim 1 , wherein the source contact electrically contacts the N-doped source region and the P-doped channel region. 
     
     
       3. The LDMOS transistor as defined by of  claim 2  and, further including a backside source contact on a surface of the N-doped substrate. 
     
     
       4. The LDMOS transistor as defined by of  claim 3 , wherein the source contact is formed in a groove extending from the surface of the P-doped epitaxial layer through the P-doped epitaxial layer and the P+ doped buried layer to the N-doped substrate, and includes a metal silicide layer formed on the surface of the groove and a filler metal filling the groove. 
     
     
       5. The LDMOS transistor as defined by of  claim 4 , wherein the filler metal comprises gold. 
     
     
       6. The LDMOS transistor as defined by of  claim 5 , wherein the metal silicide comprises a refractory metal silicide. 
     
     
       7. The LDMOS transistor as defined by of  claim 6  and, further including a gate shield overlying a portion of the gate electrode facing the N-doped drain region. 
     
     
       8. The LDMOS transistor as defined by of  claim 7 , wherein the gate shield is electrically connected to the source contact. 
     
     
       9. The LDMOS transistor as defined by of  claim 8 , wherein the gate electrode is electrically connected to the source contact by conductive ribs overlying the gate contact. 
     
     
       10. The LDMOS transistor as defined by of  claim 9  and, further including a drain contact to the N-doped drain region. 
     
     
       11. The LDMOS transistor as defined by of  claim 10 , wherein the N-doped drain region includes a lightly-doped drain region extending from a more heavily doped drain region to the channel region, the drain contact engaging the more heavily doped drain region. 
     
     
       12. The LDMOS transistor as defined by of  claim 4  and, further including a gate shield overlying a portion of the gate electrode facing the N-doped drain region. 
     
     
       13. The LDMOS transistor as defined by of  claim 12 , wherein the gate shield is electrically connected to the source contact. 
     
     
       14. The LDMOS transistor as defined by of  claim 13  and, further including a drain contact to the N-doped drain region. 
     
     
       15. The LDMOS transistor as defined by of  claim 14 , wherein the N-doped drain region includes a lightly doped drain region extending from a more heavily doped drain region to the channel region, the drain contact engaging the more heavily doped drain region. 
     
     
       16. A transistor structure comprising:
 a) aan N-doped semiconductor substrate,; 
 b) a P-doped epitaxial semiconductor layer formed on the substrate, the layer including a buried P-doped layer and having a surface,;  
 c) a source region and a drain region formed in the epitaxial layer with a channel region there between,; 
 d) a gate electrode formed on an insulator above the channel region,; and 
 e) a source contact extending from the surface of the epitaxial layer through the epitaxial layer to the N-doped semiconductor substrate, the source contact including a trench through the epitaxial layer filled with conductive material. 
 
     
     
       17. The transistor structure as defined by of  claim 16 , wherein the semiconductor substrate is grounded during device operation, the source contact extending ground to the source region. 
     
     
       18. The semiconductor structure as defined by of  claim 16 , wherein the transistor comprises a laterally diffused MOS transistor. 
     
     
       19. The transistor device as defined by structure of  claim 18 , wherein the drain region includes a heavily doped region and a lighter doped drift region extending to the channel region. 
     
     
       20. The transistor structure as defined by of  claim 19 , wherein the insulator under the gate electrode extends over the drift region. 
     
     
       21. The transistor structure as defined by of  claim 16 , wherein the conductive material is selected from the group consisting of polysilicon, a refractory metal, and a refractory metal silicide. 
     
     
       22. The transistor structure as defined by of  claim 21 , wherein said the gate electrode comprises doped polysilicon. 
     
     
       23. A device, comprising:
 a doped substrate;   a doped epitaxial layer over the doped substrate, wherein the doped epitaxial layer includes a doped buried layer;   a doped source region in the doped epitaxial layer; and   a source contact, wherein the source contact extends through the doped epitaxial layer into the doped substrate and connects the doped source region to the doped substrate.   
     
     
       24. The device of claim 23, wherein the source contact comprises a trench through the doped epitaxial layer. 
     
     
       25. The device of claim 24, wherein the trench is filled with conductive material. 
     
     
       26. The device of claim 23, wherein:
 the doped substrate is an N-doped substrate;   the doped epitaxial layer is a P-doped epitaxial layer; and   the doped source region is an N-doped source region.   
     
     
       27. The device of claim 26, wherein the doped buried layer is a P-doped buried layer. 
     
     
       28. The device of claim 23, wherein the doped buried layer is between the doped substrate and the doped epitaxial layer. 
     
     
       29. The device of claim 23, wherein the source contact extends through the doped buried layer.