Block locking apparatus for flash memory

Abstract

A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

1. A memory device comprising:
 a first flash memory array including a plurality of memory blocks each having a memory cell; 
 control circuitry coupled to the first memory array and controlling updating of the memory cells; and 
 a second independent flash memory array coupled to the control circuitry and including a plurality of block lock-bits each corresponding to one of the plurality of memory blocks, wherein each block lock-bit controls updating of the corresponding memory block. 
 
     
     
       2. The memory device of  claim 1 , wherein the memory cell is a nonvolatile memory cell. 
     
     
       3. The memory device of  claim 1 , wherein the state of each block lock-bit indicates whether data may be programmed into the memory cell in the corresponding memory block. 
     
     
       4. The memory device of  claim 1 , wherein the state of each block lock-bit indicates whether data stored in the memory cell in the corresponding memory block may be erased. 
     
     
       5. The memory device of  claim 1 , wherein the second independent flash memory array further comprises a master lock-bit, wherein the master lock-bit indicates whether the plurality of block lock-bits are locked. 
     
     
       6. The memory device of  claim 5 , wherein the memory device is configured to receive a passcode, wherein the passcode overrides the master lock-bit so as to unlock the plurality of block lock-bits. 
     
     
       7. The memory device of  claim 5 , wherein the state of the master lock-bit indicates whether the plurality of lock-bits may be programmed. 
     
     
       8. The memory device of  claim 5 , wherein the state of the master lock-bit indicates whether the plurality of lock-bits may be erased. 
     
     
       9. The memory device of  claim 1 , wherein the control circuitry controls writing the block lock-bits. 
     
     
       10. The memory device of  claim 9 , wherein the control circuitry controls erasing the block lock-bits. 
     
     
       11. The memory device of  claim 1 , wherein the control circuitry includes a master lock-bit, wherein the master lock-bit indicates whether the plurality of lock-bits are locked. 
     
     
       12. The memory device of  claim 1 , wherein the control circuitry comprises:
 a command circuit configured to receive and decode commands; 
 a write circuit coupled to the command circuit and configured to control execution of at least one of the commands; and 
 a voltage control circuit coupled to the write circuit and configured to couple program or erase voltages to the first or second memory array. 
 
     
     
       13. The memory device of  claim 1 , wherein the control circuitry further controls reading the plurality of block lock-bits. 
     
     
       14. The memory device of  claim 1 , wherein the block lock-bits each block lock-bit comprise a nonvolatile memory cell. 
     
     
       15. A memory system comprising:
 the memory device of  claim 1 ; and 
 a processing device coupled to the memory device and coupling commands to the memory device. 
 
     
     
       16. A memory system comprising:
 a memory device having a first flash memory array including a plurality of memory blocks each having a memory cell; 
 a processing device coupled to the memory device and coupling commands to the memory device; and 
 a second flash memory array coupled to the memory device and including a plurality of block lock-bits each corresponding to one of the plurality of memory blocks in the memory device, wherein each block lock-bit controls updating of the memory cell in the corresponding memory block, and wherein the block lock-bits retain their states when the memory cell in one of the memory blocks is erased. 
 
     
     
       17. The memory system of  claim 16 , wherein the second flash memory array further comprises a master lock-bit, wherein the master lock-bit indicates whether the plurality of lock-bits are locked. 
     
     
       18. The memory system of  claim 17 , wherein the memory device is configured to receive a passcode, wherein the passcode overrides the master lock-bit so as to unlock the plurality of block lock-bits.