Thin film transistor array substrate for a liquid crystal display

Abstract

A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.

1. A thin film transistor array substrate for a liquid crystal display, comprising:
 an insulating substrate;   a gate line assembly formed on the substrate, the gate line assembly having a plurality of gate lines proceeding in the horizontal direction, gate electrodes branched from the gate lines, and gate pads connected to end portions of the gate lines;   a gate insulating layer formed on the gate line assembly, the gate insulating layer having a first contact window exposing the gate pad, and an opening portion partially exposing the insulating substrate;   a semiconductor pattern formed on the gate insulating layer;   a contact pattern formed on the semiconductor pattern;   a data line assembly formed on the contact pattern with substantially the same outline as the contact pattern, the data line assembly having data lines proceeding in the vertical direction, source electrodes branched from the data lines, data pads connected to end portions of the data lines, and drain electrodes positioned opposite to the source electrodes with respect to the gate electrode while being separated from the source electrodes;   a passivation layer formed on the data line assembly with the same outline as the semiconductor pattern except at portions of a second contact window exposing the data pad and a third contact window exposing the drain electrode;   a pixel electrode formed at a pixel area defined by the neighboring gate and data lines, the pixel electrode being electrically connected to the drain electrode through the third contact window while partially contacting the gate insulating layer; and   subsidiary gate and data pads contacting the gate and data pads, respectively.   
     
     
       2. The thin film transistor array substrate of  claim 1  wherein the opening portion exposes the substrate between the pixel electrode and the neighboring data line. 
     
     
       3. The thin film transistor array substrate of  claim 1  wherein the third contact window exposing the drain electrode is extended such that the borderline of the drain electrode is exposed to the outside. 
     
     
       4. A thin film transistor array substrate for a liquid crystal display comprising:
 an insulating substrate;   a gate line assembly formed on the substrate, the gate line assembly having a plurality of gate lines proceeding in the horizontal direction, gate electrodes branched from the gate lines, and gate pads connected to end portions of the gate lines;   a first insulating layer formed on the gate line assembly, the first insulating layer having a first contact window exposing the gate pad;   a semiconductor pattern longitudinally formed on the first insulating layer in the vertical direction;   a data line assembly formed on the semiconductor pattern, the data line assembly having data lines proceeding in the vertical direction, source electrodes branched from the data lines, data pads connected to end portions of the data lines, and drain electrodes positioned opposite to the source electrodes with respect to the gate electrodes while being separated from the source electrodes;   a second insulating layer formed on the data line assembly with the same outline as the semiconductor pattern, the second insulating layer having a second contact window exposing the gate pad through the first contact window, a third contact window exposing the data pad, and a fourth contact window exposing the drain electrode;   a color filter formed at a pixel area defined by the neighboring gate and data lines; and   a pixel electrode formed on the color filter, the pixel electrode being connected to the drain electrode through the fourth contact window.   
     
     
       5. The thin film transistor array substrate of  claim 4  further comprising a contact layer formed between the semiconductor pattern and the data line assembly with the same outline as the data line assembly. 
     
     
       6. The thin film transistor array substrate of  claim 4  further comprising supplemental gate pads and supplemental data pads covering the gate pad and the data pad, respectively. 
     
     
       7. The thin film transistor array substrate of  claim 4  further comprising a photo-interceptive organic pattern formed between the data line assembly and the overlying passivation layer. 
     
     
       8. The thin film transistor array substrate of  claim 7  wherein the photo-interceptive pattern is provided with a fifth contact window exposing the drain electrode through the fourth contact window, the fifth contact window being narrower than the fourth contact window. 
     
     
       9. The thin film transistor array substrate of  claim 4  wherein the second insulating layer is formed of a photo-interceptive organic layer. 
     
     
       10. The thin film transistor array substrate of  claim 9  wherein the first insulating layer has the same outline as the semiconductor pattern. 
     
     
       11. The thin film transistor array substrate of  claim 10  wherein the opening width of the semiconductor pattern between the neighboring data lines is 1 μ or more. 
     
     
       12. A thin film transistor array substrate for a liquid crystal display, comprising:
 an insulating substrate;   a gate line assembly formed on the substrate, the gate line assembly having a plurality of gate lines proceeding in the horizontal direction, gate electrodes branched from the gate lines, and gate pads connected to end portions of the gate lines;   a first insulating layer formed on the gate line assembly, the first insulating layer having a first contact window exposing the gate pad;   a semiconductor pattern longitudinally formed on the first insulating layer in the vertical direction;   a data line assembly formed on the semiconductor pattern, the data line assembly having data lines proceeding in the vertical direction, source electrodes branched from the data lines, data pads connected to end portions of the data lines, and drain electrodes positioned opposite to the source electrodes with respect to the gate electrodes while being separated from the source electrodes, the data line assembly substantially having the same outline as the semiconductor pattern except the portion placed between the source electrode and the drain electrode;   a second insulating layer formed on the data line assembly, the second insulating layer having a second contact window exposing the first contact window, a third contact window exposing the data pad, and a fourth contact window exposing the drain electrode;   a color filter formed on the passivation layer at a pixel area defined by the neighboring gate and data lines; and   a pixel electrode formed on the color filter, the pixel electrode being connected to the drain electrode through the fourth contact window.   
     
     
       13. The thin film transistor array substrate of  claim 12  further comprising a contact layer formed between the semiconductor pattern and the data line assembly substantially with the same outline as the data line assembly. 
     
     
       14. The thin film transistor array substrate of  claim 12  further comprising supplemental gate pads and supplemental data pads covering the gate pads and the data pads, respectively. 
     
     
       15. The thin film transistor array substrate of  claim 12  further comprising a photo-interceptive organic pattern formed on the passivation layer over the data line assembly and the gate line assembly. 
     
     
       16. The thin film transistor array substrate of  claim 15  wherein the photo-interceptive organic pattern is provided with a fifth contact window exposing the drain electrode through the fourth contact window, the fifth contact window being narrower than the fourth contact window. 
     
     
       17. The thin film transistor array substrate of  claim 12  wherein the second insulating layer is formed with a photo-interceptive organic layer. 
     
     
       18. A thin film transistor array substrate for a liquid crystal display comprising:
 an insulating substrate;   a gate line assembly formed on the substrate, the gate line assembly having a plurality of gate lines proceeding in the horizontal direction, gate electrodes connected to the gate lines, and gate pads connected to end portions of the gate lines;   a first insulating layer formed on the gate line assembly, the first insulating layer having a first contact window exposing the gate pad, and an opening portion partially exposing the insulating substrate;   a semiconductor pattern formed on the first insulating layer;   a contact pattern formed on the semiconductor pattern;   a data line assembly formed on the contact pattern with substantially the same outline as the contact pattern, the data line assembly having data lines proceeding in the vertical direction, source electrodes connected to the data lines, data pads connected to end portions of the data lines, and drain electrodes positioned opposite to the source electrodes with respect to the gate electrode while being separated from the source electrodes;   a second insulating layer formed on the data line assembly with the same outline as the semiconductor pattern except at portions of a second contact window exposing the data pad and a third contact window exposing the drain electrode;   a pixel electrode formed at a pixel area defined by the neighboring gate and data lines, the pixel electrode being electrically connected to the drain electrode through the third contact window while partially contacting the first insulating layer; and   subsidiary gate and data pads contacting the gate and data pads, respectively.    
     
     
       19. The thin film transistor array substrate of claim 18, wherein the third contact window exposing the drain electrode is extended such that the borderline of the drain electrode is exposed to the outside.  
     
     
       20. The thin film transistor array substrate of claim 18, wherein the second insulating layer is the photo-interceptive layer.  
     
     
       21. The thin film transistor array substrate of claim 18, wherein the data line assembly has a double layered structure comprising a first metallic layer and a second metallic layer, and
 the first metallic layer is formed of at least one of a material such as Cr, Mo or Mo alloy, and the second metallic layer is formed of at least one of a material such as Al or Al alloy, and   the pixel electrode is electrically connected to the first metallic layer.