Imager output signal processing

Abstract

The method and apparatus for processing pixel output signals from column lines in an imager having an array of pixels in rows and columns uses a sigma-delta type analog-to-digital converter to convert the output signals on each column line to digital signals and feeding them to a digital signal processor. The converter is monitored to stop sampling of a pixel with the detection of pixel saturation, which is carried out by counting a predetermined number of consecutive zeros in the converted signal. In addition, the next pixel in a column may be controlled to be read with the saturation of the previous pixel, and the next row of pixels may be controlled to be read with the saturation of the pixels in the previous row. Further, sets of a predetermined number of converter output samples are condensed by a decimator into binary numbers of predetermined bit length. The outputs of the decimators may be fed directly to the digital signal processor or they may be multiplexed to provide one or more inputs to the digital signal processor.

1. In an imager having an array of pixels in rows and columns with column lines for pixel output signals, a method of processing the pixel output signals comprising:
 converting the pixel output signals on each column line to digital signals using a sigma-delta type analog-to-digital converter, the sigma-delta type converter outputting mainly logical ones for a high input signal level and outputting mainly zeros for a low input signal level; 
 feeding the digital signals to a digital signal processor; and 
 monitoring the sigma-delta type converter to stop sampling of a pixel when pixel saturation is detected, 
 wherein the monitoring step comprises, for each column:
 at a first counter, counting consecutive zeros in the digital signals to a predetermined number, and 
 detecting the pixel saturation in response to counting to the predetermined number at the first counter. 
 
 
     
     
       2. A method of processing the pixel output signals as claimed in  claim 1  further comprising:
 sending the sigma-delta type converter output to the digital signal processor when the pixel saturation is detected. 
 
     
     
       3. A method of processing the pixel output signals as claimed in  claim 1  further comprising:
 reading the next pixel in a column when the previous pixel is saturated. 
 
     
     
       4. A method of processing the pixel output signals as claimed in  claim 1  further comprising:
 reading the next row of pixels when the pixels in the previous row are all saturated. 
 
     
     
       5. A method of processing the pixel output signals as claimed in  claim 1  further comprising, for each column:
 condensing sets of a predetermined number of sigma-delta type converter output samples in a decimator to binary numbers of predetermined bit length. 
 
     
     
       6. A method of processing the pixel output signals as claimed in  claim 5  further comprising, for each column:
 determining the number of sigma-delta type converter output samples and outputting the determined number when the value of the first counter reaches the predetermined number; and 
 feeding the determined number from the first counter to the decimator. 
 
     
     
       7. A method of processing the pixel output signals as claimed in  claim 5  further comprising:
 determining the number of sigma-delta type converter output samples and outputting the determined number when the value of the first counter reaches the predetermined number; and 
 feeding the determined number from the first counter to the digital signal processor. 
 
     
     
       8. A method of processing the pixel output signals as claimed in  claim 5  further comprising:
 multiplexing the outputs of the decimators to provide one or more inputs to the digital signal processor. 
 
     
     
       9. In an imager having an array of pixels in rows and columns with column lines for pixel output signals, apparatus for processing the pixel output signals comprising:
 a sigma-delta type analog-to-digital converter for converting the pixel output signals on each column line to digital signals, the sigma-delta type converter outputting mainly logical ones for a high input signal level and outputting mainly zeros for a low input signal level; 
 means for feeding the digital signals to a digital signal processor; 
 means for detecting pixel saturation; and 
 means for stopping sampling of a pixel when the pixel saturation is detected, 
 wherein the detecting means comprises: 
 a first counter provided for each column for counting consecutive zeros in the digital signals to a predetermined number to determine when the pixel saturation has occurred. 
 
     
     
       10. Apparatus for processing the pixel output signals as claimed in  claim 9  further comprising:
 means for sending the sigma-delta type converter output to the digital signal processor when the pixel saturation is detected. 
 
     
     
       11. Apparatus for processing the pixel output signals as claimed in  claim 9  further comprising:
 a decimator provided for each column for condensing sets of a predetermined number of sigma-delta type converter output samples to binary numbers of predetermined bit length. 
 
     
     
       12. Apparatus for processing the pixel output signals as claimed in  claim 11  further comprising:
 means provided for each column for determining the number of sigma-delta type converter output samples and outputting the determined number when the value of the first counter reaches the predetermined number; and 
 means for feeding the determined number from the number determining means to the corresponding decimator. 
 
     
     
       13. Apparatus for processing the pixel output signals as claimed in  claim 12  wherein the number determining means is a second counter, and wherein when the second counter outputs the determined number to the corresponding decimator, the corresponding decimator outputs the binary numbers and the second counter resets to zero. 
     
     
       14. Apparatus for processing the pixel output signals as claimed in  claim 11  further comprising:
 means provided for each column for determining the number of sigma-delta type converter output samples and outputting the determined number when the value of the first counter reaches the predetermined number; and 
 means for feeding the determined number from the number determining means to the digital signal processor. 
 
     
     
       15. Apparatus for processing the pixel output signals as claimed in  claim 14 , wherein the number determining means is a second counter, and wherein when the second counter outputs the determined number to the digital signal processor, the second counter resets to zero. 
     
     
       16. Apparatus for processing the pixel output signals as claimed in  claim 11  further comprising:
 means for multiplexing the outputs of the decimators to provide one or more inputs to the digital signal processor. 
 
     
     
       17. Apparatus for processing the pixel output signals as claimed in  claim 16  wherein the multiplexing means comprises a multiplexer for providing one input line to the digital signal processor. 
     
     
       18. Apparatus for processing the pixel output signals as claimed in  claim 16  wherein the multiplexing means comprises a number of multiplexers for providing a number of input lines to the digital signal processor. 
     
     
       19. Apparatus for processing the pixel output signals as claimed in  claim 9  further comprising:
 means for reading the next pixel in a column when the previous pixel is saturated. 
 
     
     
       20. Apparatus for processing the pixel output signals as claimed in  claim 9  further comprising:
 means for reading the next row of pixels when the value of the first counter reaches the predetermined number. 
 
     
     
       21. In an imager having an array of pixels in rows and columns with column lines for pixel output signals, a method comprising:
 processing the pixel output signals on each column line using a sigma-delta type analog-to-digital converter, the sigma-delta type converter outputting digital signals comprising mainly logical ones for a high input signal level and comprising mainly zeros for a low input signal level; and   monitoring the sigma-delta type converter to stop sampling of a pixel in response to detecting pixel saturation;   wherein the monitoring step comprises, for each column:
 at a first counter, counting consecutive zeros in the digital signals to a predetermined number; and 
 detecting pixel saturation in response to counting to the predetermined number at the first counter. 
   
     
     
       22. The method of claim 21 further comprising reading a next pixel in a column in response to detecting that a previous pixel is saturated. 
     
     
       23. The method of claims 21 further comprising reading a next row of pixels in response to detecting pixels of a previous row are saturated. 
     
     
       24. The method of claim 21 further comprising, for each column,
 condensing sets of a predetermined number of sigma-delta type converter output samples in a decimator to binary numbers of predetermined bit length;   determining the number of sigma-delta type converter output samples and outputting the determined number when the value of the first counter reaches the predetermined number; and   feeding the determined number from the first counter to the decimator.   
     
     
       25. In an imager having an array of pixels in rows and columns with column lines for pixel output signals, an apparatus comprising:
 a sigma-delta type analog-to-digital converter configured to convert the pixel output signals on each column line to digital signals, wherein the sigma-delta type converter outputs mainly logical ones for a high input signal level and outputs mainly zeros for a low input signal level;   means for detecting pixel saturation; and   means for stopping sampling of a pixel in response to detecting pixel saturation;   wherein the detecting means comprises a first counter provided for each column for counting consecutive zeros in the digital signals to a predetermined number to detect pixel saturation.   
     
     
       26. The apparatus of claim 25 further comprising a decimator provided for each column, wherein the decimator is configured to condense sets of a predetermined number of sigma-delta type converter output samples to binary numbers of predetermined bit length. 
     
     
       27. The apparatus of claim 26 further comprising:
 means provided for each column for determining the number of sigma-delta type converter output samples and outputting the determined number when the value of the first counter reaches the predetermined number; and   means for feeding the determined number from the number determining means to the corresponding decimator.   
     
     
       28. The apparatus of claim 27 wherein the number determining means comprises a second counter, and wherein when the second counter outputs the determined number to the corresponding decimator, the corresponding decimator outputs the binary numbers and the second counter resets to zero. 
     
     
       29. An apparatus comprising:
 a sigma-delta type analog-to-digital converter configured to convert pixel output signals to digital signals comprising mainly logical ones for a high input signal level and mainly zeros for a low input signal level, and to stop sampling a pixel in response to detected pixel saturation; and   a saturation counter configured to count consecutive zeros in the digital signals and to detect pixel saturation in response to obtaining a predetermined count associated with pixel saturation.   
     
     
       30. The apparatus of claim 29 further comprising:
 a digital signal processor configured to determine pixel values based upon output signals; and   output circuitry configured to receive the digital signals and to provide output signals to the digital signal processor.   
     
     
       31. The apparatus of claim 29 further comprising:
 a digital signal processor configured to determine pixel values based upon binary numbers of a predetermined bit length; and   output circuitry configured to receive the digital signals and to provide output signals comprising binary numbers of the predetermined bit length to the digital signal processor, the output circuitry comprising one or more decimators configured to condense sets of a predetermined number of sigma-delta type converter output samples of the digital signals to binary numbers of the predetermined bit length.   
     
     
       32. The apparatus of claim 31 wherein the output circuitry further comprises one or more decimator counters configured to feed the one or more decimators with the predetermined number of sigma-delta type converter output samples in response to the saturation counter reaching the predetermined count. 
     
     
       33. The apparatus of claim 32, wherein the output circuitry further comprises one or more multiplexers configured to receive the binary numbers of the predetermined length from the one or more decimators and to provide to the digital signal processor with the binary numbers of the predetermined length. 
     
     
       34. The apparatus of claim 29 further comprising
 a digital signal processor configured to determine pixel values based upon a predetermined number of sigma-delta type output samples of the digital signals; and   output circuitry configured to provide the predetermined number of sigma-delta type output samples to the digital signal processor, the output circuitry comprising one or more decimator counters configured to feed the digital signal processor with the predetermined number of sigma-delta type output samples in response to the saturation counter reaching the predetermined count.   
     
     
       35. The apparatus of claim 34, wherein the output circuitry further comprises one or more multiplexers configured to receive the predetermined number of sigma-delta type output samples and to provide the predetermined number of sigma-delta type output samples to the digital signal processor. 
     
     
       36. The apparatus of claim 29, wherein in response to detecting pixel saturation, the saturation counter provides a feedback that results in the sigma-delta type analog-to-digital converter reading a next pixel in a column of pixels. 
     
     
       37. The apparatus of claim 29, further comprising
 a plurality of sigma-delta type analog-to-digital converters, each sigma-delta type analog-to-digital converter configured to convert pixel output signals for a column of pixels to digital signals comprising mainly logical ones for a high input signal level and mainly zeros for a low input signal level, and to stop sampling a pixel in response to detected pixel saturation;   a plurality of saturation counters, each saturation counter configured to count consecutive zeros in the digital signals and to detect pixel saturation in response to reaching the predetermined count associated with pixel saturation;   row enable circuitry to select a next row of pixels for reading by the plurality of sigma-delta type analog-to-digital converters in response to a result that indicates that each of the plurality of saturation counters detected pixel saturation; and   a comparator to receive outputs from each of the plurality of saturation counters and to provide the row enable circuitry with the result in response to determining based upon the received outputs that each of the plurality of saturation counters detected pixel saturation.   
     
     
       38. An apparatus comprising:
 an array of pixels in rows and columns;   a plurality of column lines to carry pixel output signals;   one or more sigma-delta type analog-to-digital converters, each of the one more sigma-delta analog-to-digital converters configured to convert pixel output signals to digital signals comprising mainly logical ones for a high input signal level and mainly zeros for a low input signal level, and to stop converting pixel output signals of a pixel in response to detected saturation of the pixel;   column output circuitry configured to receive the digital signals and to feed output signals to a digital signal processor; and   a plurality of saturation counters configured to detect pixel saturation, each saturation counter configured to count consecutive zeros in the digital signals of a corresponding column line, and to detect saturation in response to reaching a predetermined count.   
     
     
       39. The apparatus of claim 38 further comprising a digital signal processor configured to determine pixel values based upon the output signals of the column output circuitry. 
     
     
       40. The apparatus of claim 39 further comprising a digital signal processor configured to determine pixel values based upon binary numbers of a predetermined bit length, wherein the column output circuitry is configured to provide output signals comprising binary numbers of the predetermined bit length to the digital signal processor, the column output circuitry comprising a plurality of decimators configured to condense sets of a predetermined number of sigma-delta type converter output samples of the digital signals to binary numbers of the predetermined bit length. 
     
     
       41. The apparatus of claim 40 wherein the column output circuitry further comprises a plurality decimation counters configured to feed a corresponding decimator of the plurality of decimators with the predetermined number of sigma-delta type converter output samples in response to corresponding saturation counters reaching the predetermined number. 
     
     
       42. The apparatus of claim 41, wherein the column output circuitry further comprises a multiplexer configured to receive outputs from the plurality of decimators and to provide the outputs of the plurality of decimators to the digital signal processor. 
     
     
       43. The apparatus of claim 39, wherein in response to detecting pixel saturation, a saturation counter of the plurality of saturation counters provides a feedback that results in a corresponding sigma-delta type analog-to-digital converter reading a next pixel in a column of pixels. 
     
     
       44. The apparatus of claim 39, further comprising
 row enable circuitry configured to select a next row of pixels for reading by the plurality of sigma-delta type analog-to-digital converters in response to a result that indicates that each of the plurality of saturation counters detected pixel saturation; and   a comparator configured to receive outputs from each of the plurality of saturation counters and to provide the row enable circuitry with the result in response to determining based upon the received outputs that each of the plurality of saturation counters detected pixel saturation.