Single substrate camera device with CMOS image sensor

Abstract

Single substrate device is formed to have an image acquisition device and a controller. The controller on the substrate controls the system operation.

1. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and further comprising double sampling charge storage elements on said substrate. 
 
     
     
       2. A camera device as in  claim 1 , wherein said timing circuit includes a timer for first sampling a reset level on a first of said charge storage elements, and then for second sampling a signal level on a second of said charge storage elements. 
     
     
       3. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said array of photoreceptors are controlled to output an entire row of said photoreceptors substantially simultaneously; and 
 a plurality of double sampling charge storage elements integrated on said substrate; one for each of said columns. 
 
     
     
       4. A camera device as in  claim 3 , wherein said timing circuit includes a timer for first sampling all reset levels in a specific column on first charge storage elements, and then for second sampling all signal levels on second charge storage elements. 
     
     
       5. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired colum column for read out, and a row selector which allows selection of a desired row fro for readout. 
 
     
     
       6. A camera device as in  claim 5 , wherein said row selector includes a latch element, storing a value for a row to be selected, and a counter, allowing incrementing of said value to read a next consecutive row, said latch element and said counter both being integrated in said substrate. 
     
     
       7. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, 
 wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout, 
 wherein said row selector includes a latch element, storing a value for a row to be selected, and a counter, allowing incrementing of said value to read a next consecutive row, said latch element and said counter both being integrated on said substrate. 
 
     
     
       8. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreeptors photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout, wherein said colum column selector includes presettable start and stop column decoder counters, which are preset to start and stop at any desired value. 
 
     
     
       9. A camera device as in  claim 8 , further comprising an input data bus, connected to the camera device, values on said data bus being used to preset said start and stop column decoder counters. 
     
     
       10. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a mode selector device, selecting a mode of operation of said chip, 
 wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and second mode of operation, different that said first mode of operation, for operation with photodiodes. 
 
     
     
       11. A camera device as in  claim 10 , further comprising a differencing mode which alters readout timing in such a way that the value of each pixel output represents a difference between a current frame and a previous frame. 
     
     
       12. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and 
 further comprising a correlated double sampling circuit. 
 
     
     
       13. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, 
 wherein said timing circuit controls readout from said chip in a correlated double sampling mode. 
 
     
     
       14. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that a least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, 
 wherein said timing circuit allows changing an integration time for said array of photoreceptors. 
 
     
     
       15. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and 
 further comprising fixed pattern noise reduction circuits, on said substrate. 
 
     
     
       16. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a noise reduction circuit, 
 wherein said timing circuit times an operation of said noise reduction circuit to occur during a time of the video signal which is not being displayed. 
 
     
     
       17. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that a least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit. 
 
     
     
       18. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a mode selector device, selecting a mode of operation of said chip, 
 wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and second mode of operation, different that said first mode of operation, for operation with photodiodes. 
 
     
     
       19. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing present of at least one of a start address for output or a stop address for output; 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors. 
 
     
     
       20. A camera device as in  claim 19 , wherein said signal controlling device includes a column-parallel read out device, which reads out a row of said photoreceptors at substantially the same time. 
     
     
       21. A camera device as in  claim 20 , wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout. 
     
     
       22. A camera device as in  claim 19 , further comprising an input data bus, connected to the camera device, values on said data bus being used to preset said start and stop values. 
     
     
       23. A camera device as in  claim 19 , wherein said photoreceptors are photodiodes. 
     
     
       24. A camera device as in  claim 19 , wherein said photoreceptors are photogates. 
     
     
       25. A camera device as in  claim 19 , wherein said photoreceptors are either photogates or photodiodes, further comprising a mode selector device which selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes. 
     
     
       26. A camera device as in  claim 25 , further comprising a differencing mode which alters readout timing in such a way that the value of each pixel output represents a difference between a current frame and a previous frame. 
     
     
       27. A camera device as in  claim 19 , further comprising a correlated double sampling circuit integrated on the chip. 
     
     
       28. A camera device as in  claim 19 , wherein said timing circuit controls readout from said chip in a correlated double sampling mode. 
     
     
       29. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output; 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor. 
 
     
     
       30. A camera device as in  claim 29 , wherein said readout amplifier is preferably within and/or associated with one element of the array. 
     
     
       31. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output; 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit. 
 
     
     
       32. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output; 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit. 
 
     
     
       33. A camera device as in  claim 32 , wherein said timing circuit times an operation of said noise reduction circuit to occur during a time of the video signal which is not being displayed. 
     
     
       34. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors in a first mode or in a second mode, depending on a type of photoreceptor being used. 
 
     
     
       35. A camera device as in  claim 34 , wherein said photoreceptor is one of a photodiode or a photogate, and said array is controlled into said first mode for said photogate and in said second mode for said photodiode. 
     
     
       36. A camera device as in  claim 35 , further comprising a correlated double sampling circuit. 
     
     
       37. A camera device as in  claim 35 , further comprising a differencing mode which alters readout timing in such a way that the value of each pixel output represents a difference between a current frame and a previous frame. 
     
     
       38. A camera device as in  claim 35 , wherein said timing circuit allows changing an integration time for said array of photoreceptors. 
     
     
       39. A camera device as in  claim 38 , wherein said timing circuit times an operation of said noise reduction circuit to occur during a time of the video signal which is not being displayed. 
     
     
       40. A camera device as in  claim 34 , wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor. 
     
     
       41. A camera device as in  claim 40 , wherein said readout amplifier is preferably within and/or associated with one element of the array. 
     
     
       42. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors in a first mode or in a second mode, depending on a type of photoreceptor being used, further comprising a noise reduction circuit. 
 
     
     
       43. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, 
 said control portion including common logic elements to control row and address decoders and delay counters. 
 
     
     
       44. A camera device as in  claim 43 , wherein said signal controlling device includes a column-parallel read out device, which reads out a column of said photoreceptors at substantially the same time. 
     
     
       45. A camera device as in  claim 44 , further comprising a noise reduction circuits, on chip. 
     
     
       46. A camera device as in  claim 45 , wherein said timing circuit times an operation of said noise reduction circuit to occur during a time of the video signal which is not being displayed. 
     
     
       47. A camera device as in  claim 45 , wherein said noise reduction circuit is a fixed pattern noise reduction circuit. 
     
     
       48. A camera device as in  claim 45 , wherein said noise reduction circuit is a column to column fixed pattern noise reduction circuit. 
     
     
       49. A camera device as in  claim 43 , wherein said signal controlling device includes a column selector allowing selection of a desired row for read out, and a row selector which allows selection of a desired row for readout. 
     
     
       50. A camera device as in  claim 49  wherein said row selector includes a latch element, storing a value for a row to be selected, and a counter, allowing incrementing of said value to read a next consecutive row, said latch element and said counter both being integrated on said substrate. 
     
     
       51. A camera device as in  claim 49 , wherein said column selector includes presettable start and stop column decoder counters, which are preset to start and stop at any desired value. 
     
     
       52. A camera device as in  claim 51 , further comprising an input data bus, connected to the camera device, values on said data bus being used to preset said start and stop column decoder counters. 
     
     
       53. A camera device as in  claim 43 , wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor. 
     
     
       54. A camera device as in  claim 53 , wherein said readout amplifier is preferably within and/or associated with one element of the array. 
     
     
       55. A camera device as in  claim 53 , wherein said photoreceptors are photodiodes. 
     
     
       56. A camera device as in  claim 53  wherein said photoreceptors are photogates. 
     
     
       57. A camera device as in  claim 43 , further comprising a correlated double sampling circuit. 
     
     
       58. A camera device as in  claim 43 , wherein said timing circuit controls readout from said chip in a correlated double sampling mode. 
     
     
       59. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, 
 said control portion including common logic elements to control row and address decoders and delay counters, further comprising a mode selector device, selecting a mode of operation of said chip. 
 
     
     
       60. A camera device as in  claim 59 , wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes. 
     
     
       61. A camera device as in  claim 60 , further comprising a differencing mode which alters readout timing in such a way that the value of each pixel output represents a difference between a current frame and a previous frame. 
     
     
       62. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output; 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors. 
 
     
     
       63. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in row and columns; 
 a charge storage element, associated with each said columns; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; 
 said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously, further comprising a mode selector device, selecting a mode of operation of said chip. 
 
     
     
       64. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in rows and columns; 
 a charge storage element, associated with each said colum column; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, 
 said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously, 
 wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes. 
 
     
     
       65. A single chip camera device, comprising:
 a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; 
 said image acquisition portion integrated in said substrate including an array of photoreceptors; 
 said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output; 
 said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors. 
 
     
     
       66. A method of controlling a single chip camera, comprising:
 integrating, on a single substrate, an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS, said image acquisition portion integrated in said substrate including an array of photoreceptors, and a signal controlling device, controlling said photoreceptors and a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; 
 determining a first mode of operation for said photoreceptors being photogates, and a second mode of operation for said photoreceptors being photodiodes; 
 using said on-chip timing and control circuit to control sequences for accessing rows in a specified order depending on said mode of operation, using a first sequence for said first mode of operation for photogates, and a second mode of operation for said second mode for photodiodes, a timing for said first mode being different than a timing for said second mode.