Method and device for configuration of PLDS

Abstract

A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

1. A Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation, comprising:
 an array of configuration memory cells; 
 a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells; 
 a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells; 
 a Horizontal Shift Register (HSR) providing the an enable input to the Select Register (SR); and 
 a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR. 
 
     
     
       2. The Programmable Logic Device of  claim 1  wherein the Configuration State Machine comprises:
 an index register that specifies the a number of columns of the configuration array that are to be enabled; 
 an increment register that contains the a number of shifts required in the HSR prior to enabling the column; and 
 a count address register that provides a count of the number of programmed columns. 
 
     
     
       3. The Programmable Logic Device of  claim 1  wherein the Horizontal Shift Register comprises a plurality of flip-flops connected in series to form a serial shift register with a common clock signal and initialization signal that sets the first flip-flop and clears the remaining flip-flops at the start of the configuration process. 
     
     
       4. A device, comprising:
 a configurable memory latch array; 
 a vertical shift register supplying configuration data to rows of the array; and 
 a circuit for moving the configuration data from the vertical shift register to one a selected column of the array for storage, the circuit comprising:
 a horizontal select register operable to select columns within the array; 
 a horizontal shift register generating control signals driving horizontal select register operation; and 
 a configuration state machine controlling operation of the horizontal shift register. 
 
 
     
     
       5. The device of  claim 4  wherein the configuration state machine comprises:
 an index register which registers a number of columns to be enabled from a current column specified by the horizontal shift register; 
 an increment register which registers a number of shifts until selection of a column by the horizontal shift register; and 
 a count address register which registers a count for each completed operation of moving configuration data from the vertical shift register. 
 
     
     
       6. The device of  claim 4  wherein the configuration state machine comprises:
 an index register specifying a number of columns of the array that are to be loaded with configuration data; 
 an increment register specifying a number of shifts required by the horizontal shift register before enabling a desired column; and 
 a count address register specifying a count of completed operations to move configuration data from the vertical shift register. 
 
     
     
       7. A device comprising:
 a configurable memory latch array; 
 a vertical shift register supplying configuration data to rows of the array; 
 a horizontal shift register; and 
 a configuration state machine including;
 an index register which registers a number of columns to be enabled from a current column specified by the horizontal shift register; 
 an increment register which registers a number of shifts until selection of a column by the horizontal shift register; and 
 a count address register which registers a count for each completed operation of moving configuration data from the vertical shift register. 
 
 
     
     
       8. A device comprising:
 a configurable memory latch array; 
 a vertical shift register supplying configuration data to rows of the array; 
 a horizontal shift register; and 
 a configuration state machine including:
 an index register specifying a number of columns of the array that are to be loaded with configuration data; 
 an increment register specifying a number of shifts required by the horizontal shift register before enabling a desired column; and 
 a count address register specifying a count of completed operations to move configuration data from the vertical shift register. 
 
 
     
     
       9. A Programmable Logic Device comprising:
 a select register;   a horizontal shift register configured to provide an enable input to the select register; and   a configuration state machine configured to control operation of the horizontal shift register.   
     
     
       10. The Programmable Logic Device as recited in claim 9, wherein the configuration state machine includes an increment register that is configured to contain a number of shifts used by the horizontal shift register prior to enabling a column in a configurable memory latch array on the programmable logic device. 
     
     
       11. The Programmable Logic Device as recited in claim 9, wherein the configuration state machine comprises:
 an index register configured to specify a number of columns of a configuration array that are to be enabled;   an increment register configured to contain a number of shifts used by the horizontal shift register prior to enabling the column; and   a count address register configured to provide a count of a number of programmed columns.   
     
     
       12. The Programmable Logic Device as recited in claim 9, wherein the horizontal shift register comprises a plurality of flip-flops connected in series to form a serial shift register with a common clock signal and initialization signal that is configured to set a first flip-flop and clear remaining flip-flops at the start of a configuration process. 
     
     
       13. The Programmable Logic Device as recited in claim 9, further comprising an array of configuration memory cells operably associated with the select register. 
     
     
       14. The Programmable Logic Device as recited in claim 9, further comprising:
 an array of configuration memory cells operably associated with the select register; and   a vertical shift register operably associated with the array of configuration memory cells.   
     
     
       15. The Programmable Logic Device as recited in claim 14, wherein the vertical shift register is connected to vertical lines of the array of configuration memory cells. 
     
     
       16. The Programmable Logic Device as recited in claim 13, wherein the select register is configured to select columns within the array of configuration memory cells. 
     
     
       17. The Programmable Logic Device as recited in claim 13, wherein the select register is connected to horizontal lines of the array of configuration memory cells. 
     
     
       18. A Programmable Logic Device comprising:
 a configuration state machine; and   a horizontal shift register comprising a plurality of registers, wherein the horizontal shift register is scalably configurable to remove or add one or more of the plurality of registers, and wherein the plurality of registers are configured to receive an initialize signal and a clock signal from the configuration state machine.   
     
     
       19. The Programmable Logic Device as recited in claim 18, wherein the initialize signal is configured to set a first register in the plurality of registers and clear remaining registers in the plurality of registers. 
     
     
       20. The Programmable Logic Device as recited in claim 19, wherein the plurality of registers comprise a plurality of flip-flops connected in series to form a serial shift register with a common clock signal and initialization signal that is configured to set a first flip-flop and clear remaining flip-flops at the start of a configuration process. 
     
     
       21. The Programmable Logic Device as recited in claim 18, wherein the configuration state machine is configured to control the operation of the horizontal shift register. 
     
     
       22. The Programmable Logic Device as recited in claim 18, further comprising a select register, wherein the configuration state machine is configured to control the operation of the horizontal shift register, and wherein the horizontal shift register is configured to provide an enable input to the select register. 
     
     
       23. A method comprising:
 changing a memory array size of a Programmable Logic Device by performing one or more of:
 adding a register to a horizontal shift register of the Programmable Logic Device, or 
 removing a register from the horizontal shift register; 
   wherein the Programmable Logic Device includes a configuration state machine.   
     
     
       24. A method for configuring a Programmable Logic Device comprising:
 clearing a memory associated with the Programmable Logic Device;   loading contents of index and increment registers into the memory;   shifting a horizontal shift register by a value of the increment register;   incrementing a count address register by the value of the increment register;   decrementing the value of the increment register by a value of one;   repeating said shifting, incrementing and decrementing until the value of the increment register is equal to zero;   generating a select enable signal from a configuration state machine to the select register;   initiating the horizontal shift register by sending a clock signal from the configuration state machine to the horizontal shift register; and   decrementing values of the index and increment registers by one.   
     
     
       25. A method for configuring a Programmable Logic Device comprising:
 loading contents of index and increment registers into a memory associated with the Programmable Logic Device;   shifting a horizontal shift register by a value of the increment register;   incrementing a count address register by the value of the increment register;   decrementing the value of the increment register by a value of one;   repeating said shifting, incrementing, and decrementing until the value of the increment register is equal to zero;   generating a select enable signal from a configuration state machine to a select register;   initiating the horizontal shift register by sending a clock signal from the configuration state machine to the horizontal shift register; and   decrementing values of the index and increment registers by one.   
     
     
       26. A device comprising:
 a configurable memory latch array;   a vertical shift register supplying configuration data to rows of the array;   a circuit configured to move the configuration data from the vertical shift register to a selected column of the array for storage, the circuit including a scalable plurality of registers, wherein the circuit is scalable by adding or removing one or more of the plurality of registers; and   a configuration state machine configured to control operation of the circuit, the configuration state machine including an index register, an increment register, and a count address register.   
     
     
       27. A Programmable Logic Device comprising:
 a horizontal shift register;   a configuration state machine configured to control the horizontal shift register; and   means for enabling the Horizontal Shift Register to provide an enable input to an associated Select Register.   
     
     
       28. A Programmable Logic Device comprising:
 a configurable memory latch array including a plurality of columns;   a horizontal shift register;   a configuration state machine including an increment register configured to register a count value of a number of horizontal shift register shifts that are used before enabling a first line of the horizontal shift register, wherein the increment register is configured to enable partial configuration of the configurable memory latch array starting from any column in the plurality of columns in the memory latch array.