Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing

Abstract

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D 1 ” is decoded, the sum-product result register 6 outputs its held value to the path P 1 . The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21 , the zero value “0x0000_0000” generated by the zero generator 25 , and the held value of the sum-product result register 6 to the data bus 18.

1. A processor that decodes and executes instructions,
 the processor comprising:   a detecting unit for detecting whether an instruction to be decoded is a predetermined instruction; and   a rounding unit for rounding, when the detecting unit is detecting that the instruction is the predetermined instruction, a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer wherein s is less than m.   
     
     
       2. The processor of  claim 1 , wherein the predetermined instruction includes a transfer address of a value rounded by the rounding unit, and the rounding unit includes:
 a first judging circuit for judging, when the detecting unit is detecting that the instruction is the predetermined instruction, whether a signed m-bit integer stored at the operand is a negative number; and   a second judging circuit for judging when the detecting unit is detecting that the instruction is the predetermined instruction, whether a signed m-bit integer stored at the operand exceeds a maximum value expressed as an unsigned s-bit integer, and   wherein the processor further comprises:   transferring unit for transferring one of a first predetermined value expressed as an unsigned s-bit integer a second predetermined value expressed as an unsigned s-bit integer, and a value stored at the operand to the transfer address for a rounding result, based on the combination of respective judging results of the first judging circuit and the second judging circuit.   
     
     
       3. The processor of  claim 2 ,
 wherein the transferring unit transfers a value zero expressed as an s-bit integer as the first predetermined value to the transfer address for the rounding result, when the first judging circuit judges that the signed m-bit integer stored at the operand is a negative number;   wherein the transferring unit transfers the maximum value expressed as an unsigned s-bit integer as a second predetermined value to the transfer address for the rounding result, when the second judging circuit judges that the signed m-bit integer stored at the operand exceeds the maximum value expressed as an unsigned s-bit integer, and   wherein the transferring unit transfers the value stored at the operand to the transfer address for the rounding result, when the first judging circuit judges that the signed m-bit integer stored at the operand is not a negative number and the second judging circuit judges that the signed m-bit integer stored at the operand does not exceed the maximum value.   
     
     
       4. The processor of  claim 3 ,
 wherein the first judging circuit includes a judging unit for judging whether a sign bit of an s-bit integer in the signed m-bit integer stored at the operand is on or off, and   wherein the second judging circuit includes a calculator for subtracting a maximum positive value for an s-bit integer from the signed m-bit integer stored at the operand.   
     
     
       5. The processor of  claim 4 , wherein m-bit is 32 bits in size and the predetermined instruction includes an indication field indicating one of 8 bits, 16 bits, and 24 bits as s-bit,
 wherein the judging unit of the first judging circuit examines one of an eighth, sixteenth, and twenty-fourth bit counted from a least significant bit side as the sign bit, in accordance with a content of the indication field included in the predetermined instruction, and   wherein the second judging circuit includes a generating unit for generating one of an unsigned 8-bit integer, and an unsigned 16-bit integer, and an unsigned 24-bit integer, in accordance with a content of the indication field included in the predetermined instruction.   
     
     
       6. The processor of  claim 2 , further comprising a specialized register and a calculation unit for performing a calculation in the instruction sequence and adding a calculation result to a value held by the specialized register,
 wherein the predetermined instruction designates the specialized register as the operand, and   the transferring unit transfers the value stored in the specialized register to the transfer address for the rounding result, when the first judging circuit judges that a signed m-bit integer stored in the specialized register is not a negative number and the second judging circuit judges that the signed m-bit integer stored in the specialized register does not exceed the maximum value.   
     
     
       7. The processor of  claim 6 , further comprising a register file composed of a plurality of general registers,
 wherein the predetermined instruction designates one of the general registers in the register file as a transfer address for a rounding result, and   wherein the transferring unit transfers one of a first predetermined value express as an unsigned s-bit integer, a second predetermined value expressed as an unsigned s-bit integer, and a value stored in the specialized register to the general register being designated by the predetermined instruction.   
     
     
       8. A processor that decodes and executes instructions,
 the processor comprising: 
 first detecting unit for detecting whether an instruction to be decoded is an instruction performing a calculation; 
 second detecting unit for detecting whether an instruction to be decoded is an instruction performing both a calculation and a rounding of the calculation result; 
 calculating unit for performing, when the first detecting unit detects that the instruction performs a calculation, a calculation using a signed m-bit integer; and 
 rounding unit for rounding, when the second detecting unit detects the instruction performing both a calculation and a rounding, a result of the calculation performed with a signed m-bit integer to a value expressed as an unsigned s-bit integer wherein s is less than m. 
 
     
     
       9. The processor of  claim 8 , wherein the instruction performing both a calculation and a rounding further includes an indication of a transfer address for a rounding result,
 and wherein the rounding unit includes: 
 a first judging circuit for judging, when the second detecting unit detects the instruction performing both a calculation and a rounding, whether the calculation result of the calculating unit is a negative number; and 
 a second judging circuit for judging, when the second detecting unit detects that the instruction performing both a calculation and a rounding, whether the calculation result of the calculating unit exceeds a maximum value expressed as an unsigned s-bit integer, and 
 wherein the processor further comprises: 
 transferring unit for transferring one of a first predetermined value expressed as an unsigned s-bit integer, a second predetermined value expressed as an unsigned s-bit integer, and the calculation result of the calculating unit to the transfer address, based on the combination of respective judging results of the first judging circuit and the second judging circuit. 
 
     
     
       10. The processor of  claim 9 ,
 wherein the transferring unit transfers a value zero expressed as an s-bit integer as the first predetermined value to the transfer address, when the first judging circuits judges that the calculation result of the calculating unit is a negative number; 
 wherein the transferring unit transfers the maximum value expressed as an unsigned s-bit integer as the second predetermined value to the transfer address, when the second judging circuit judges that the calculation result of the calculating unit exceeds the maximum value expressed as an unsigned s-bit integer; and 
 wherein the transferring unit transfers the calculation result of the calculating unit to the transfer address for the rounding result, when the first judging circuit judges that the calculation result of the calculating unit is not a negative number and the second judging circuit judges that the calculation result of the calculating unit does not exceed the maximum value. 
 
     
     
       11. The processor of  claim 10 , wherein the first judging circuit includes a judging unit for judging whether a sign bit of the calculation result of the calculating unit is on or off, and
 wherein the second judging circuit includes a calculator for subtracting a maximum positive value for an unsigned s-bit integer from the calculation result of the calculation unit. 
 
     
     
       12. The processor of  claim 11 , wherein m bits is 32 bits in size and the correction instruction includes an indication field indicating one of 8 bits, 16 bits, and 24 bits as s bits,
 wherein the judging unit of the first judging circuit examines one of an eighth, sixteenth, and twenty-fourth bit from a least significant bit as the sign bit, in accordance with a content of the indication field included in the correction instruction, and 
 wherein the calculator includes a generating unit for generating one of an unsigned 8-bit integer, an unsigned 16-bit integer, and an unsigned 24-bit integer, in accordance with a content of the indication field included in a correction instruction. 
 
     
     
       13. The processor of  claim 12 , further comprising a register file composed of a plurality of general registers,
 wherein each calculation instruction designates one of the general registers in the register file as a transfer address for a rounding result. 
 
     
     
       14. A machine readable medium storing a program that enables a processor for executing a rounding process comprising:
 detection step for directing the processor for detecting whether an instruction to be decoded by the processor is a predetermined instruction; and   rounding step for directing the processor for rounding a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer wherein s is less than m.   
     
     
       15. A program recording medium that enables a processor to decode and execute instructions comprising:
 first direction for directing the processor to detect whether an instruction to be decoded is an instruction for performing a calculation; 
 second direction for directing the processor to detect whether an instruction to be decoded is an instruction performing both a calculation and a rounding of the calculation result; 
 third direction for directing the processor to perform, when the processor detects that the instruction performs a calculation, a calculation using a signed m-bit integer; and 
 fourth direction for directing the processor, when the processor is detecting an instruction performing both a calculation and a rounding, for rounding a result of the calculation performed with a signed m-bit integer to a value expressed as an unsigned s-bit integer wherein s is less than m. 
 
     
     
       16. The program recording medium of  claim 15  further including fifth direction for directing the processor to designate a register as a transfer address for a rounding result. 
     
     
       17. The program recording medium of  claim 16  wherein the fourth direction includes:
 a first judging step for judging, when the processor detects the instruction performing both a calculation and a rounding, whether the calculation result of the calculating means is a negative number; and 
 a second judging step for judging, when the processor detects that the instruction performing both a calculation and a rounding, whether the calculation result of the calculating means exceeds a maximum value expressed as an unsigned s-bit integer, and 
 transferring step for directing the processor to transfer one of a first predetermined value expressed as an unsigned s-bit integer, a second predetermined value expressed as an unsigned s-bit integer, and the calculation result of the calculating data to the transfer address, based on the combination of respective judging results of the first judging step and the second judging step. 
 
     
     
       18. The program recording medium of  claim 17  wherein the transferring step directs the processor to transfer a value zero expressed as an s-bit integer as the first predetermined value to the transfer address, when the first judging data judges that the calculation result of the calculating data is a negative number,
 wherein the transferring step directs the processor to transfer the maximum value expressed as an unsigned s-bit integer as the second predetermined value to the transfer address, when the second judging step judges that the calculation result of the calculating data exceeds the maximum value expressed as an unsigned s-bit integer; and 
 wherein the transferring step directs the processor to transfer the calculation result of the calculating data to the transfer address for the rounding result, when the first judging step judges that the calculation result of the calculating data is not a negative number and the second judging step judges that the calculation result of the calculating data does not exceed the maximum value. 
 
     
     
       19. The processor of  claim 18 , wherein the first judging step directs the processor to determine whether a sign bit of the calculation result of the calculating data is on or off, and
 wherein the second judging step directs the processor to subtract a maximum positive value for an unsigned s-bit integer from the calculation result of the calculation data. 
 
     
     
       20. The program recording medium of  claim 19 , wherein m-bit is 32 bits in size and the fourth direction includes an indication field indicating one of 8 bits, and 24 bits as s bits,
 wherein the first judging step directs the processor to examine one of an eighth, sixteenth, and twenty-fourth bit from a least significant bit as the sign bit, in accordance with a content of the indication field, 
 wherein the second judging step directs the processor to generate one of an unsigned 8-bit integer, an unsigned 16-bit integer, and an unsigned 24-bit integer, in accordance with a content of the indication field. 
 
     
     
       21. The processor of claim 8,
 wherein the value of s is specified by the instruction performing both a calculation and a rounding.   
     
     
       22. The program recording medium of claim 15,
 wherein the value of s is specified by the instruction performing both a calculation and a rounding.   
     
     
       23. A processor comprising:
 a decoder that receives an instruction causing the processor to execute an operation comprising:
 (1) converting a signed input operand to zero when the operand is negative, and 
 (2) saturating the operand to a maximum value when the operand exceeds the maximum value; and 
   a circuit that executes the operation, wherein   the maximum value is specified with an opcode for the instruction, and is not specified by an operand for the instruction.   
     
     
       24. The processor of claim 23, wherein the instruction designates the operand. 
     
     
       25. The processor of claim 24,
 wherein the operation further comprises (3) truncating the operand when the operand is neither negative nor exceeds the maximum value.   
     
     
       26. The processor of claim 25,
 wherein the operand is a signed integer, each of the maximum value and the truncated operand is an unsigned integer, and available range of the signed integer entirely includes an available range of the unsigned integer.   
     
     
       27. The processor of claim 26,
 wherein the signed integer is m-bit long and the unsigned integer is s-bit long, wherein s is less than m.   
     
     
       28. The processor of claim 24, wherein the circuit includes
 a zero generator for outputting data having a zero value, and   a constant generator for outputting data of the maximum value.   
     
     
       29. The processor of claim 28, wherein the circuit further includes a selection unit for
 selecting the output of the zero generator when the operand designated by the instruction is negative, and   selecting the output of the constant generator when the operand exceeds the maximum value.   
     
     
       30. The processor of claim 29,
 wherein the selection unit selects one of the output of the zero generator, the output of the constant generator, and a value obtained by truncating the operand designated by the instruction, when the operand is neither negative nor exceeds the maximum value.   
     
     
       31. The processor of claim 24,
 wherein the operand designated by the instruction is a result of executing a second instruction which is different from the instruction.   
     
     
       32. The processor of claim 23,
 wherein the operation further comprises:
 (3) truncating the operand when the operand is neither negative nor exceeds the maximum value; and 
   wherein the circuit includes
 a zero generator for outputting a value zero represented as an s-bit integer, 
 a constant generator for outputting data of the maximum value represented as an unsigned s-bit integer, 
 a truncating unit for truncating the operand designated by the instruction and which is represented as a signed m-bit integer, to an unsigned s-bit value, s being less than m, and 
 a selection unit for a) selecting the output of the zero generator, when the operand designated by the instruction is negative, b) selecting the output of the constant generator, when the operand exceeds the maximum value, and c) selecting the output of the truncating unit, when the operand is neither negative nor exceeds the maximum value. 
   
     
     
       33. The processor of claim 23,
 wherein the maximum value is specified by the instruction.   
     
     
       34. A processor that decodes and executes instructions, the processor comprising:
 a calculating unit for calculating; and   a positive conversion and saturation calculation unit for
 a) converting a data to zero when the data is negative, and 
 b) saturating a data to a maximum value when the data exceeds the maximum value, 
   wherein the positive conversion and saturation calculation unit converts or saturates data provided by the calculating unit, and the calculating together with one of the converting and the saturating are performed by one instruction,   wherein the positive conversion and saturation calculation unit includes
 a zero generator for outputting a data having a zero value, and 
 a constant generator for outputting data of the maximum value, 
   wherein the positive conversion and saturation calculation unit further includes a selection unit for
 a) selecting the output of the zero generator when the data provided by the calculating unit is negative, and 
 b) selecting the output of the constant generator, when the data exceeds the maximum value, 
   wherein the selection unit selects one of the output of the zero generator, the output of the constant generator, and a value obtained by truncating the data provided by the calculating unit, when the data provided by the calculating unit is neither negative nor exceeds the maximum value,   wherein the positive conversion and saturation calculation unit further includes:
 a polarity judging unit for detecting whether the data designated by the one instruction is negative; and 
 a comparator for detecting whether the data exceeds the maximum value, and 
   wherein the selection unit
 a) selects the output of the zero generator when the polarity judging unit has detected that the data is negative, 
 b) selects the output of the constant generator when the comparator has detected that the data exceeds the maximum value, and 
 c) selects the output of the truncating unit when neither the polarity judging unit has detected that the data is negative nor the comparator has detected that the data exceeds the maximum value. 
   
     
     
       35. The processor of claim 34,
 wherein the maximum value is specified by the one instruction.   
     
     
       36. A processor comprising:
 a decoder that receives an instruction causing the processor to execute an operation comprising:
 (1) performing a calculation upon a signed input operand to generate a result, 
 (2) converting the result to zero when the result is negative, and 
 (3) saturating the result to a maximum value when the result exceeds the maximum value; and 
   a circuit that executes the operation.   
     
     
       37. The processor of claim 36, wherein the instruction designates the operand. 
     
     
       38. The processor of claim 37,
 wherein the operation further comprises (4) truncating the result when the result is neither negative nor exceeds the maximum value.   
     
     
       39. The processor of claim 38,
 wherein the operand is a signed integer, each of the maximum value and the truncated operand is an unsigned integer, and an available range of the signed integer entirely includes an available range of the unsigned integer.   
     
     
       40. The processor of claim 39,
 wherein the signed integer is m-bit long and the unsigned integer is s-bit long, wherein s is less than m.   
     
     
       41. The processor of claim 36,
 wherein the operation further comprises:
 (4) truncating the result when the result is neither negative nor exceeds the maximum value; 
   wherein the operand is represented as a signed m-bit integer; and   wherein the circuit includes
 a zero generator that outputs a value zero represented as an s-bit integer, 
 a constant generator that outputs data of the maximum value represented as an unsigned s-bit integer, 
 a truncating unit that truncates the result to an unsigned s-bit value, s being less than m, and 
 a selection unit that
 a) selects the output of the zero generator, when the result is negative, 
 b) selects the output of the constant generator, when the result exceeds the maximum value, and 
 c) selects the output of the truncating unit, when the result is neither negative nor exceeds the maximum value. 
 
   
     
     
       42. The processor of claim 41,
 wherein the circuit further includes
 a polarity judging unit for detecting whether the result is negative, and 
 a comparator for detecting whether the result exceeds the maximum value, 
   wherein the selection unit
 a) selects the output of the zero generator, when the polarity judging unit has detected that the result is negative, 
 b) selects the output of the constant generator, when the comparator has detected that the result exceeds the maximum value, and 
 c) selects the output of the truncating unit, when neither the polarity judging unit has detected that the result is negative, nor the comparator has detected that the result exceeds the maximum value. 
   
     
     
       43. The processor of claim 36,
 wherein the circuit includes
 a zero generator for outputting data having a zero value; and 
 a constant generator for outputting data of the maximum value. 
   
     
     
       44. The processor of claim 43,
 wherein the circuit further includes a selection unit for
 a) selecting the output of the zero generator when the result is negative, and 
 b) selecting the output of the constant generator when the result exceeds the maximum value. 
   
     
     
       45. The processor of claim 44,
 wherein the selection unit selects one of the output of the zero generator, the output of the constant generator, and a value obtained by truncating the result, when the result is neither negative nor exceeds the maximum value.   
     
     
       46. The processor of claim 36,
 wherein the maximum value is specified by the instruction.   
     
     
       47. A processor that decodes and executes instructions, the processor comprising:
 a decoding unit for decoding an instruction including a certain instruction, the certain instruction designating a signed data; and   a positive conversion and saturation calculation unit for a) converting the data to zero when the data is negative, and for b) saturating the data to a maximum value when the data exceeds the maximum value,   wherein the converting and the saturating are selectively performed in response to decoding of the certain instruction performed at the decoding unit, and   wherein the maximum value is specified with an opcode for the instruction, and is not specified by an operand for the instruction.   
     
     
       48. A processor that decodes and executes instructions, the processor comprising:
 a decoding unit for decoding an instruction including a certain instruction, the certain instruction designating a signed data;   a calculating unit for performing calculations using the data designated by the certain instruction to produce output data; and   a positive conversion and saturation calculation unit for a) converting the output data provided by the calculating unit to zero when the output data is negative, and b) saturating the output data provided by the calculating unit to a maximum value when the output data exceeds the maximum value;   wherein the calculating together with either the converting or the saturating are performed in response to decoding of the certain instruction performed at the decoding unit.   
     
     
       49. The processor of claim 48,
 wherein the maximum value is specified by the certain instruction.   
     
     
       50. A processor that decodes and executes instructions, the processor comprising:
 a decoding unit for detecting whether an instruction to be decoded is a certain instruction; and   a rounding unit for rounding, when the decoding unit is detecting that the instruction is the certain instruction, a signed m-bit integer stored at an operand designated by the certain instruction to a value expressed as an unsigned s-bit integer wherein s is less than m, wherein   the value of s is specified by an opcode for the instruction, and is not specified by an operand for the instruction.   
     
     
       51. The processor of any one of claims 23-32, wherein the circuit executes the operation within a single execution cycle. 
     
     
       52. The processor of any one of claims 36-45, wherein the circuit executes the operation in a single cycle.