Semiconductor memory module, electronic apparatus and method for operating thereof

Abstract

A semiconductor memory module ( 1 ) includes a circuit substrate ( 2 ), a first ( 100 ), a second ( 200 ), a third ( 300 ) and a fourth ( 400 ) rank of memory chips ( 3 ), a first register ( 10 ) and a second register ( 20 ). The first register ( 10 ) and the second register ( 20 ) each comprise a first input ( 11, 21 ) for receiving a respective chip select signal (CS 0, CS 2 ), a second input ( 12, 22 ) for receiving a respective other chip select signal (CS 1, CS 3 ) at least one third input ( 13, 23 ) for receiving command/address signals (CA), and at least one third output ( 16, 26 ). The at least one third output ( 16, 26 ) of the respective first ( 10 ) and second ( 20 ) register transmits the command/address signals (CA), if at least one of the respective chip select signal (CS 0, CS 2 ) received at the respective first input ( 11, 21 ) of the respective register ( 10, 20 ) and the respective other chip select signal (CS 1, CS 3 ) received at the respective second input ( 12, 22 ) of the respective register ( 10, 20 ) is active, and blocks a transmission of the command/address signals (CA), if both the respective chip select signal (CS 0, CS 2 ) received at the respective first input ( 11, 21 ) of the respective register ( 10, 20 ) and the respective other chip select signal (CS 1, CS 3 ) received at the respective second input ( 12, 22 ) of the respective register ( 10, 20 ) are inactive.

1. A semiconductor memory module comprising:
 a circuit substrate; 
 a first, a second, a third and a fourth rank of memory chips each rank including a plurality of memory chips and each being disposed on said circuit substrate; 
 a first register and a second register each disposed on said circuit substrate, said first register and said second register each comprising:
 a first input for receiving a an associated first chip select signal having one of an active or an inactive level; 
 a second input for receiving a other an associated second chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated first chip select signal to said memory chips of said first rank and or said third rank, said first output of said first register coupled to transmit said associated first chip select signal to said memory chips of said first rank and said first output of said second register coupled to transmit said associated first chip select signal to said memory chips of said third rank; 
 a second output coupled to transmit said other associated second chip select signal to said memory chips of said second rank and or said fourth rank, said second output of said first register coupled to transmit said associated second chip select signal to said memory chips of said second rank and said second output of said second register coupled to transmit said associated second chip select signal to said memory chips of said fourth rank; and 
 at least one third output for outputting command/address signals, wherein said at least one third output of said first register is coupled to transmit said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if at least one of said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register is active, and to block a transmission of said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if both said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register are inactive; and 
 said at least one third output of said second register is coupled to transmit said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register is active, and to block a transmission of said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if both said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register are inactive. 
 
 
     
     
       2. The semiconductor memory module according to  claim 1 , wherein said circuit substrate has a first surface and a second surface, wherein said first register and said memory chips of said first rank are disposed on said first surface and said memory chips of said second rank are stacked upon said memory chips of said first rank, and wherein
 said second register and said memory chips of said third rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said memory chips of said third rank. 
 
     
     
       3. The semiconductor memory module according to  claim 1 , wherein said circuit substrate comprises an edge connector having contacts for transmitting electrical signals between said circuit substrate and an external device. 
     
     
       4. The semiconductor memory module according to  claim 3 , wherein ends of said contacts are coupled via respective conductive lines disposed on said circuit substrate to said first input, to said second input and to said at least one third input of each of said first register and said second register. 
     
     
       5. The semiconductor memory module according to  claim 4 , wherein said electrical signals comprise said associated first chip select signals, said other associated second chip select signals and said command/address signals. 
     
     
       6. The semiconductor memory module according to  claim 1 , wherein each of said first register and said second register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 said at least one third output of said first register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register is active, and to block said command/address signals, if said control signal is active and if both said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register are inactive; 
 said at least one third output of said first register coupled to transmit said command/address signals, if said control signal is inactive; 
 said at least one third output of said second register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register is active, and to block said command/address signals, if said control signal is active and if both said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register are inactive; and 
 said at least one third output of said second register coupled to transmit said command/address signals if said control signal is inactive. 
 
     
     
       7. The semiconductor memory module according to  claim 1 , wherein said semiconductor module has a socket disposed on said circuit substrate, said semiconductor memory module further comprising:
 another circuit substrate having a plug disposed thereon; 
 a fifth, a sixth, a seventh, and an eighth rank of memory chips each including a plurality of memory chips and each being disposed on said other circuit substrate; 
 a third register and a fourth register each disposed on said other circuit substrate, said third register and said fourth register each comprising:
 a first input for receiving a an associated third chip select signal having one of an active or an inactive level; 
 a second input for receiving a an associated fourth chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated third chip select signal to said memory chips of said fifth rank and or said seventh rank, said first output of said third register coupled to transmit said associated third chip select signal to said memory chips of said fifth rank and said first output of said fourth register coupled to transmit said associated third chip select signal to said memory chips of said seventh rank; 
 a second output coupled to transmit said associated fourth chip select signal to said memory chips of said sixth rank and or said eighth rank, said second output of said third register coupled to transmit said associated fourth chip select signal to said memory chips of said sixth rank and said second output of said fourth register coupled to transmit said associated second chip select signal to said memory chips of said eighth rank; and 
 at least one third output, wherein said socket of said circuit board and said plug of said other circuit board are coupled and provide an electrical connection for the transmission of said associated first chip select signal signals, said other associated second chip select signal signals, said associated third chip select signal signals, said associated fourth chip select signal signals and said command/address signal signals between said circuit board and said other circuit board; 
 said at least one third output of said third register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and 
 said at least one third output of said fourth register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive. 
 
 
     
     
       8. The semiconductor memory module according to  claim 7 , wherein said other circuit substrate has a first surface and a second surface, wherein said third register, said memory chips of said fifth rank and said memory chips of said sixth rank are disposed on said first surface, and wherein
 said fourth register, said memory chips of said seventh rank and said memory chips of said eighth rank are disposed on said second surface. 
 
     
     
       9. The semiconductor memory module according to  claim 7 , wherein each of said third register and said fourth register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 said at least one third output of said third register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; 
 said at least one third output of said third register coupled to transmit said command/address signals, if said control signal is inactive; 
 said at least one third output of said fourth register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive; and 
 said at least one third output of said fourth register coupled to transmit said command/address signals if said control signal is inactive. 
 
     
     
       10. The semiconductor memory module according to  claim 1 , wherein said memory chips comprise dynamic random access memory chips. 
     
     
       11. The semiconductor memory module according to  claim 1 , wherein said memory chips comprise synchronous dynamic random access memory chips. 
     
     
       12. The semiconductor memory module according to  claim 1 , wherein said semiconductor memory module comprises a dual inline memory module. 
     
     
       13. An electronic apparatus comprising:
 a controller device; 
 a bus system; 
 at least one semiconductor memory module comprising:
 a circuit substrate; 
 a first, a second, a third and a fourth rank of memory chips each rank including a plurality of memory chips and each being disposed on said circuit substrate; 
 a first register and a second register each disposed on said circuit substrate, said first register and said second register each comprising:
 a first input coupled to said controller device for receiving a an associated first chip select signal having one of an active or an inactive level; 
 a second input coupled to said controller device for receiving a other an associated second chip select signal having one of an active or an inactive level; 
 at least one third input coupled to said controller device via said bus system for receiving command/address signals; 
 a first output coupled to transmit said associated first chip select signal to said memory chips of said first rank and or said third rank, said first output of said first register coupled to transmit said associated first chip select signal to said memory chips of said first rank and said first output of said second register coupled to transmit said associated first chip select signal to said memory chips of said third rank; 
 a second output coupled to transmit said other associated second chip select signal to said memory chips of said second rank and or said fourth rank, said second output of said first register coupled to transmit said associated second chip select signal only to said memory chips of said second rank and said second output of said second register coupled to transmit said associated second chip select signal only to said memory chips of said fourth rank; and 
 at least one third output for outputting command/address signals, wherein said at least one third output of said first register is coupled to transmit said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if at least one of said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register is active, and to block a transmission of said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if both said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register are inactive; and 
 said at least one third output of said second register is coupled to transmit said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register is active, and to block a transmission of said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if both said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register are inactive. 
 
 
 
     
     
       14. The electronic apparatus according to  claim 13 , wherein said circuit substrate has a first surface and a second surface, wherein said first register and said memory chips of said first rank are disposed on said first surface and said memory chips of said second rank are stacked upon said memory chips of said first rank, and wherein
 said second register and said memory chips of said third rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said memory chips of said third rank. 
 
     
     
       15. The electronic apparatus according to  claim 13 , wherein said circuit substrate comprises an edge connector having contacts for transmitting electrical signals between said circuit substrate and an external device. 
     
     
       16. The electronic apparatus according to  claim 15 , wherein ends of said contacts are coupled via respective conductive lines disposed on said circuit substrate to said first input, to said second input and to said at least one third input of each of said first register and said second register. 
     
     
       17. The electronic apparatus according to  claim 16 , wherein said electrical signals comprise said associated first chip select signals, said other associated second chip select signals and said command/address signals. 
     
     
       18. The electronic apparatus according to  claim 13 , wherein each of said first register and said second register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 said at least one third output of said first register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register is active, and to block said command/address signals, if said control signal is active and if both said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register are inactive; 
 said at least one third output of said first register coupled to transmit said command/address signals, if said control signal is inactive; 
 said at least one third output of said second register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register is active, and to block said command/address signals, if said control signal is active and if both said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register are inactive; and 
 said at least one third output of said second register coupled to transmit said command/address signals if said control signal is inactive. 
 
     
     
       19. The electronic apparatus according to  claim 13 , wherein said semiconductor module has a socket disposed on said circuit substrate, said semiconductor memory module further comprising:
 another circuit substrate having a plug disposed thereon; 
 a fifth, a sixth, a seventh, and an eighth rank of memory chips each including a plurality of memory chips and each being disposed on said other circuit substrate; 
 a third register and a fourth register each disposed on said other circuit substrate, said third register and said fourth register each comprising:
 a first input coupled to said controller device for receiving a an associated third chip select signal having one of an active or an inactive level; 
 a second input coupled to said controller device for receiving a an associated fourth chip select signal having one of an active or an inactive level; 
 at least one third input coupled to said controller device via said bus system for receiving command/address signals; 
 a first output coupled to transmit said associated third chip select signal to said memory chips of said fifth rank and or said seventh rank, said first output of said third register coupled to transmit said associated third chip select signal only to said memory chips of said fifth rank and said first output of said fourth register coupled to transmit said associated third chip select signal only to said memory chips of said seventh rank; 
 a second output coupled to transmit said associated fourth chip select signal to said memory chips of said sixth rank and or said eighth rank, said second output of said third register coupled to transmit said associated fourth chip select signal only to said memory chips of said sixth rank and said second output of said fourth register coupled to transmit said associated second chip select signal only to said memory chips of said eighth rank; and 
 at least one third output, wherein said socket of said circuit board and said plug of said other circuit board are coupled and provide an electrical connection for the transmission of said associated first chip select signal signals, said other associated second chip select signal signals, said associated third chip select signal signals, said associated fourth chip select signal signals and said command/address signal signals between said circuit board and said other circuit board; 
 said at least one third output of said third register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and 
 said at least one third output of said fourth register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive. 
 
 
     
     
       20. The electronic apparatus according to  claim 19 , wherein said other circuit substrate has a first surface and a second surface, wherein said third register, said memory chips of said fifth rank and said memory chips of said sixth rank are disposed on said first surface, and wherein
 said fourth register, said memory chips of said seventh rank and said memory chips of said eighth rank are disposed on said second surface. 
 
     
     
       21. The electronic apparatus according to  claim 19 , wherein each of said third register and said fourth register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 said at least one third output of said third register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; 
 said at least one third output of said third register coupled to transmit said command/address signals, if said control signal is inactive; 
 said at least one third output of said fourth register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive; and 
 said at least one third output of said fourth register coupled to transmit said command/address signals if said control signal is inactive. 
 
     
     
       22. The electronic apparatus according to  claim 13 , wherein said memory chips comprise dynamic random access memory chips. 
     
     
       23. The electronic apparatus according to  claim 13 , wherein said memory chips comprise synchronous dynamic random access memory chips. 
     
     
       24. The electronic apparatus according to  claim 13 , wherein said semiconductor memory module comprises a dual inline memory module. 
     
     
       25. A method of operating a semiconductor memory module, said method comprising:
 providing a semiconductor memory module comprising:
 a circuit substrate; 
 a first, a second, a third and a fourth rank of memory chips each rank including a plurality of memory chips and each being disposed on said circuit substrate; 
 a first register and a second register each disposed on said circuit substrate, said first register and said second register each comprising:
 a first input for receiving a an associated first chip select signal having one of an active or an inactive level; 
 a second input for receiving a other an associated second chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated first chip select signal to said memory chips of said first rank and or said third rank, said first output of said first register coupled to transmit said associated first chip select signal only to said memory chips of said first rank and said first output or said second register coupled to transmit said associated first chip select signal only to said memory chips of said third rank; 
 a second output coupled to transmit said other associated second chip select signal to said memory chips of said second rank and or said fourth rank, said second output of said first register coupled to transmit said associated second chip select signal only to said memory chips of said second rank and said second output of said second register coupled to transmit said associated second chip select signal only to said memory chips of said fourth rank; and 
 at least one third output for outputting command/address signals; 
 determining if one of said associated first chip select signals and one of said other associated second chip select signals is active; 
 transmitting said command/address signals to said memory chips of said first rank and to said memory chips of said second rank via said at least one third output of said first register if at least one of said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register is active, and to block a transmission of said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if both said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register are inactive; and 
 transmitting said command/address signals via said at least one third output of said second register to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register is active, and to block a transmission of said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if both said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register are inactive. 
 
 
 
     
     
       26. The method according to  claim 25 , wherein said circuit substrate has a first surface and a second surface, wherein said first register and said memory chips of said first rank are disposed on said first surface and said memory chips of said second rank are stacked upon said memory chips of said first rank, and wherein
 said second register and said memory chips of said third rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said memory chips of said third rank. 
 
     
     
       27. The method according to  claim 25 , wherein said circuit substrate comprises an edge connector having contacts for transmitting electrical signals between said circuit substrate and an external device. 
     
     
       28. The method according to  claim 27 , wherein ends of said contacts are coupled via respective conductive lines disposed on said circuit substrate to said first input, to said second input and to said at least one third input of each of said first register and said second register. 
     
     
       29. The method according to  claim 28 , wherein said electrical signals comprise said chip select signals, said other chip select signals and said command/address signals. 
     
     
       30. The method according to  claim 25 , wherein each of said first register and said second register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 said at least one third output of said first register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register is active, and to block said command/address signals, if said control signal is active and if both said associated first chip select signal received at said first input of said first register and said other associated second chip select signal received at said second input of said first register are inactive; 
 said at least one third output of said first register coupled to transmit said command/address signals, if said control signal is inactive; 
 said at least one third output of said second register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register is active, and to block said command/address signals, if said control signal is active and if both said associated first chip select signal received at said first input of said second register and said other associated second chip select signal received at said second input of said second register are inactive; and 
 said at least one third output of said second register coupled to transmit said command/address signals if said control signal is inactive. 
 
     
     
       31. The method according to  claim 25 , wherein said semiconductor module has a socket disposed on said circuit substrate, said semiconductor memory module further comprising:
 another circuit substrate having a plug disposed thereon; 
 a fifth, a sixth, a seventh, and an eighth rank of memory chips each including a plurality of memory chips and each being disposed on said other circuit substrate; 
 a third register and a fourth register each disposed on said other circuit substrate, said third register and said fourth register each comprising:
 a first input for receiving a an associated third chip select signal having one of an active or an inactive level; 
 a second input for receiving a an associated fourth chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated third chip select signal to said memory chips of said fifth rank and or said seventh rank, said first output of said third register coupled to transmit said associated third chip select signal only to said memory chips of said fifth rank and said first output of said fourth register coupled to transmit said associated third chip select signal only to said memory chips of said seventh rank; 
 a second output coupled to transmit said associated fourth chip select signal to said memory chips of said sixth rank and or said eighth rank, said second output of said third register coupled to transmit said associated fourth chip select signal only to said memory chips of said sixth rank and said second output of said fourth register coupled to transmit said associated second chip select signal only to said memory chips of said eighth rank; and 
 at least one third output, wherein said socket of said circuit board and said plug of said other circuit board are coupled and provide an electrical connection for the transmission of said associated first chip select signal signals, said other associated second chip select signal signals, said associated third chip select signal signals, said associated fourth chip select signal signals and said command/address signal signals between said circuit board and said other circuit board; 
 
 said at least one third output of said third register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and 
 said at least one third output of said fourth register is coupled to transmit said command/address signals, if at least one of said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive. 
 
     
     
       32. The method according to  claim 31 , wherein said other circuit substrate has a first surface and a second surface, wherein said third register, said memory chips of said fifth rank and said memory chips of said sixth rank are disposed on said first surface, and wherein
 said fourth register, said memory chips of said seventh rank and said memory chips of said eighth rank are disposed on said second surface. 
 
     
     
       33. The method according to  claim 31 , wherein each of said third register and said fourth register comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 said at least one third output of said third register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; 
 said at least one third output of said third register coupled to transmit said command/address signals, if said control signal is inactive; 
 said at least one third output of said fourth register coupled to transmit said command/address signals, if said control signal is active and if at least one of said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register is active, and to block said command/address signals, if said control signal is active and if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive; and 
 said at least one third output of said fourth register coupled to transmit said command/address signals if said control signal is inactive. 
 
     
     
       34. The method according to  claim 25 , wherein said memory chips comprise dynamic random access memory chips. 
     
     
       35. The method according to  claim 25 , wherein said memory chips comprise synchronous dynamic random access memory chips. 
     
     
       36. The method according to  claim 25 , wherein said semiconductor memory module comprises a dual inline memory module. 
     
     
       37. A semiconductor memory module comprising:
 a circuit substrate;   a first, a second, a third and a fourth rank of memory chips each rank including a plurality of memory chips and each being disposed on said circuit substrate;   a first register disposed on said circuit substrate, said first register comprising:
 a first input for receiving an associated first chip select signal having one of an active or an inactive level; 
 a second input for receiving an associated second chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated first chip select signal to said memory chips of said first rank; 
 a second output coupled to transmit said associated second chip select signal to said memory chips of said second rank; and 
 at least one third output for outputting command/address signals coupled to transmit said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if at least one signal of a group of signals consisting of (1) said associated first chip select signal received at said first input of said first register and (2) said associated second chip select signal received at said second input of said first register is active, and to block a transmission of said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if both said associated first chip select signal received at said first input of said first register and said associated second chip select signal received at said second input of said first register are inactive; and 
   a second register disposed on said circuit substrate, said second register comprising:
 a first input for receiving an associated first chip select signal having one of an active or an inactive level; 
 a second input for receiving an associated second chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated first chip select signal to said memory chips of said third rank; 
 a second output coupled to transmit said associated second chip select signal to said memory chips of said fourth rank; and 
 at least one third output coupled to transmit said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one signal of a group of signals consisting of (1) said associated first chip select signal received at said first input of said second register and (2) said associated second chip select signal received at said second input of said second register is active, and to block a transmission of said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if both said associated first chip select signal received at said first input of said second register and said associated second chip select signal received at said second input of said second register are inactive. 
   
     
     
       38. The semiconductor memory module according to claim 37, wherein said circuit substrate has a first surface and a second surface, wherein said first register and said memory chips of said first rank are disposed on said first surface and said memory chips of said second rank are stacked upon said memory chips of said first rank, and wherein said second register and said memory chips of said third rank are disposed on said second surface and said memory chips of said fourth rank are stacked upon said memory chips of said third rank. 
     
     
       39. The semiconductor memory module according to claim 37, wherein said circuit substrate comprises an edge connector having contacts for transmitting electrical signals between said circuit substrate and an external device. 
     
     
       40. The semiconductor memory module according to claim 39, wherein ends of said contacts are coupled via respective conductive lines disposed on said circuit substrate to said first input, to said second input and to said at least one third input of each of said first register and said second register. 
     
     
       41. The semiconductor memory module according to claim 40, wherein said electrical signals comprise said associated first chip select signals, said associated second chip select signals and said command/address signals. 
     
     
       42. The semiconductor memory module according to claim 37, wherein said first register and said second register each further comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 wherein, when said control signal is active, said first register couples said at least one third output of said first register to transmit said command/address signals to said first and second rank of memory chips when at least one signal of a group of signals consisting of (1) said associated first chip select signal received at said first input of said first register and (2) said associated second chip select signal received at said second input of said first register is active and blocks said command/address signals from being transmitted to said first and second rank of memory chips when both said associated first chip select signal received at said first input of said first register and said associated second chip select signal received at said second input of said first register are inactive, and, when said control signal is inactive, said first register couples said at least one third output of said first register to transmit said command/address signals to said first and second rank of memory chips; and   wherein, when said control signal is active, said second register couples said at least one third output of said second register to transmit said command/address signals to said third and fourth rank of memory chips when at least one signal of a group of signals consisting of (1) said associated first chip select signal received at said first input of said second register and (2) said associated second chip select signal received at said second input of said second register is active and blocks said command/address signals from being transmitted to said third and fourth rank of memory chips when both said associated first chip select signal received at said first input of said second register and said associated second chip select signal received at said second input of said second register are inactive, and, when said control signal is inactive, said second register couples said at least one third output of said second register to transmit said command/address signals to said third and fourth rank of memory chips.   
     
     
       43. The semiconductor memory module according to claim 37, wherein said semiconductor module has a socket disposed on said circuit substrate, said semiconductor memory module further comprising:
 another circuit substrate having a plug disposed thereon;   a fifth, a sixth, a seventh, and an eighth rank of memory chips each including a plurality of memory chips and each being disposed on said other circuit substrate;   a third register disposed on said other circuit substrate comprising:
 a first input for receiving an associated third chip select signal having one of an active or an inactive level; 
 a second input for receiving an associated fourth chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated third chip select signal to said memory chips of said fifth rank; 
 a second output coupled to transmit said associated fourth chip select signal to said memory chips of said sixth rank; and 
 at least one third output coupled to transmit said command/address signals to said fifth and sixth rank of memory chips, if at least one signal of a group of signals consisting of (1) said associated third chip select signal received at said first input of said third register and (2) said associated fourth chip select signal received at said second input of said third register is active and to block said command/address signals from being transmitted to said fifth and sixth rank of memory chips, if both said associated third chip select signal received at said first input of said third register and said associated fourth chip select signal received at said second input of said third register are inactive; and 
   a fourth register disposed on said other circuit substrate comprising:
 a first input for receiving an associated third chip select signal having one of an active or an inactive level; 
 a second input for receiving an associated fourth chip select signal having one of an active or an inactive level; 
 at least one third input for receiving command/address signals; 
 a first output coupled to transmit said associated third chip select signal to said memory chips of said fifth rank and said seventh rank; 
 a second output coupled to transmit said associated fourth chip select signal to said memory chips of said sixth rank and said eighth rank; and 
 at least one third output coupled to transmit said command/address signals to said seventh and eighth rank of memory chips, if at least one signal of a group of signals consisting of (1) said associated third chip select signal received at said first input of said fourth register and (2) said associated fourth chip select signal received at said second input of said fourth register is active and to block said command/address signals from being transmitted to said seventh and eighth rank of memory chips, if both said associated third chip select signal received at said first input of said fourth register and said associated fourth chip select signal received at said second input of said fourth register are inactive; 
   wherein said socket of said circuit board and said plug of said other circuit board are coupled and provide an electrical connection for the transmission of said associated first chip select signals, said associated second chip select signals.   
     
     
       44. The semiconductor memory module according to claim 43, wherein said other circuit substrate has a first surface and a second surface, wherein said third register, said memory chips of said fifth rank and said memory chips of said sixth rank are disposed on said first surface, and wherein said fourth register, said memory chips of said seventh rank and said memory chips of said eighth rank are disposed on said second surface. 
     
     
       45. The semiconductor memory module according to claim 43, wherein said third register and said fourth register each comprises a fourth input for receiving a control signal having one of an active and an inactive level;
 wherein, when said control signal is active, said third register couples said at least one third output of said third register to transmit said command/address signals to said fifth and sixth rank of memory chips when at least one signal of a group of signals consisting of (1) said associated first chip select signal received at said first input of said third register and (2) said associated second chip select signal received at said second input of said third register is active and blocks said command/address signals from being transmitted to said fifth and sixth rank of memory chips when both said associated first chip select signal received at said first input of said third register and said associated second chip select signal received at said second input of said third register are inactive, and, when said control signal is inactive, said third register couples said at least one third output of said third register to transmit said command/address signals to said fifth and sixth rank of memory chips; and   wherein, when said control signal is active, said fourth register couples said at least one third output of said fourth register to transmit said command/address signals to said seventh and eighth rank of memory chips when at least one signal of a group of signals consisting of (1) said associated first chip select signal received at said first input of said fourth register and (2) said associated second chip select signal received at said second input of said fourth register is active and blocks said command/address signals from being transmitted to said seventh and eighth rank of memory chips when both said associated first chip select signal received at said first input of said fourth register and said associated second chip select signal received at said second input of said fourth register are inactive, and, when said control signal is inactive, said fourth register couples said at least one third output of said fourth register to transmit said command/address signals to said seventh and eighth rank of memory chips.   
     
     
       46. The semiconductor memory module according to claim 37, wherein said memory chips comprise dynamic random access memory chips. 
     
     
       47. The semiconductor memory module according to claim 37, wherein said memory chips comprise synchronous dynamic random access memory chips. 
     
     
       48. The semiconductor memory module according to claim 37, wherein said semiconductor memory module comprises a dual inline memory module.