ESD protection design with turn-on restraining method and structures

Abstract

The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

What is claimed is: 
     
       1. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure comprising:
 a substrate of a first conductivity type forming that forms a base for said semiconductor structure; 
 a first region of a second conductivity type within said substrate for forming that forms a drain of a first MOS transistor; 
 a second region of the second conductivity type within said substrate for forming that forms a source of the first MOS transistor; 
 a third region of the second conductivity type within said substrate for forming that forms a source of a second MOS transistor, wherein and  
 a fourth pick up diffusion region of the first conductivity type is disposed between the second region of said first MOS transistor and the third region of said second MOS transistor for between the second region of said first MOS transistor and the third region of said second MOS transistor, wherein the pick up diffusion region surrounding surrounds said first MOS transistor with an additional laterally, wherein said second MOS transistor is not included within the pick up diffusion region, wherein the pick up diffusion region is configured to restrain the a turn on of said first MOS transistor; and 
 wherein the a channel length of said first MOS transistor is longer than the a channel length of said second MOS transistor to increase the a drain base voltage of said first MOS transistor. 
 
     
     
       2. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure comprising:
 a substrate of a first conductivity type forming that forms a base for said semiconductor structure; 
 a first region of a second conductivity type with said substrate for forming that forms a drain of a first MOS transistor; 
 a second region of he the second conductivity type within said substrate for forming that forms a source of the first MOS transistor; 
 a third region of the second conductivity type within said substrate for forming that forms a source of a second MOS transistor, wherein 
 a fourtha first pick up diffusion region of the first conductivity type is disposed between the second region ofdisposed between the second region of the first MOS transistor and the third region of the second MOS transistor, wherein the first pick up diffusion region surrounds said first MOS transistor and the third region of said second MOS transistor for surrounding said first MOS transistor with an additional pick up diffusion to restrain thelaterally, wherein the first pick up diffusion region does not surround said second MOS transistor, wherein the first pick up diffusion region is configured to restrain a turn on of said first MOS transistor;,  
 a first channel region disposed between said first and second regions of said first MOS transistor; and 
 a second channel region disposed adjacent to said third region of said second MOS transistor, wherein said a first channel length of said first channel region is longer than the a channel length of said second channel region to increase the a drain base breakdown voltage of said first MOS transistor. 
 
     
     
       3. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor substrate comprising:
 a substrate of a first conductivity type that forming forms a base for said semiconductor structure; 
 a pair of first regions of a second conductivity type within said substrate for defining that define a first channel region of the second conductivity type for a first MOS transistor; 
 a pair of second regions of the second conductivity type within said substrate for defining  that defines a second channel region of the second conductivity type for a second MOS transistor, wherein the a channel length of said first channel region is greater than the a channel length of said second channel region to reduce a turn on speed of said first MOS transistor; and 
 a pick up diffusion region of the first conductivity type that surrounds said first MOS transistor on four sides, wherein the second MOS transistor is not surrounded by the pick up diffusion region, the pick up diffusion region including a third region of the first conductivity type between thea source side of said first regions and thea source side of said second regions for surrounding said first MOS transistor with an additional pick up diffusion to further restrain the a turn on speed of said first MOS transistor. 
 
     
     
       4. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure comprising:
 a p type substrate of forming that forms a base for said semiconductor structure; 
 a first N+ region within said substrate for forming that forms a drain of a first MOS transistor; 
 a second N+ region within said substrate for forming that forms a source of the first MOS transistor; 
 a third N+ region within said substrate for forming that forms a source of a second MOS transistor, and 
 a P+ region forming a pick up diffusion region having a first portion that surrounds said first MOS transistor laterally and does not surround the second MOS transistor, wherein a the P+ region is disposed between the second N+ region of said first MOS transistor and the third N+ region of said second MOS transistor for surrounding said first MOS transistor with an additional to provide a side of the pick up diffusion to restrain the turn on speed of said first MOS transistor, and 
 wherein the a channel length of said first MOS transistor is longer than the a channel length of said second MOS transistor to increase a drain base breakdown voltage of said first MOS transistor. 
 
     
     
       5. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure comprising:
 a p type substrate of forming that forms a base for said semiconductor structure; 
 a first N+ region within said substrate for forming that forms a drain of a first MOS transistor; 
 a second N+ region within said substrate for forming that forms a source of the first MOS transistor; 
 a third N+ region within said substrate for forming that forms a source of a second MOS transistor, and 
 a P+ region that forms a pick up diffusion region, wherein a first portion of the pick up diffusion region surrounds said first MOS transistor on four sides, wherein said second MOS transistor is not located within the first portion of the pick up diffusion region, wherein a side of the P+ region is disposed between the second N+ region of said first MOS transistor and the third N+ region of said second MOS transistor for surrounding said first MOS transistor with an additional pick up providing a portion of the pick up diffusion to region for restrain restraining the a turn on speed of said first MOS transistor; 
 a first n channel region having a first channel length and disposed between said first and second regions of said first MOS transistor; and 
 a second n channel region having a second channel length disposed adjacent to said third region of said second MOS transistor, 
 wherein said first channel length is longer than said second channel length to further increase the a drain base breakdown voltage of said first MOS transistor. 
 
     
     
       6. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure comprising:
 a p type substrate forming that forms a base for said semiconductor structure; 
 a pair of first N+ regions within said substrate for defining that defines a first n channel region for a first MOS transistor; 
 a pair of second N+ regions within said substrate for defining that defines a second n channel region for a second MOS transistor, wherein the a channel length of said first channel is greater than the a channel length of said second channel; and 
 a third P+ region that defines first and second pick up diffusion regions, wherein said first pick up diffusion region surrounds said first MOS transistor laterally and wherein said second pick up diffusion region surrounds said second MOS transistor laterally, wherein a portion of the P+ region is part of said first and said second pick up diffusion regions and is disposed between the a source region of said first N+ regions and the a source region of said second N+ regions for surrounding said to separate the first MOS transistor from the second MOS transistor and for providing said first MOS transistor with an additional the first pick up diffusion to further restrain the a turn on of said first MOS transistor. 
 
     
     
       7. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure connected between an input pad and an internal circuit of said integrated circuit, said semiconductor structure comprising:
 a substrate of a first conductivity type forming that forms a base for said semiconductor structure; 
 a first channel formed between a pair of first regions of a second conductivity type within said substrate for a first MOS transistor; and 
 a second channel formed between formed between a pair of second regions of a second conductivity type within said substrate for a second MOS transistor, and  
 wherein an additionala pick up diffusion region that laterally surrounds an area that includes said first MOS transistor and does not include said second MOS transistor, wherein a portion of the pick up diffusion region is disposed between the source region of said first regions and the source region of said second regions for surrounding said first MOS transistor with an additionalto provide a portion of the pick up diffusion tofor restrain restraining thea turn on of said first MOS transistor, 
 wherein the a channel length of said first channel is longer than the a channel length of said second channel to increase a drain base breakdown voltage of said first MOS transistor. 
 
     
     
       8. A semiconductor structure for electrostatic discharge (ESD) protection of a high voltage tolerant I/O cells with stacked NMOS or PMOS integrated circuit, said semiconductor structure connected between a pre driver circuit and an input/output pad of said integrated circuit and, said semiconductor structure comprising:
 a substrate of a first conductivity type forming a base for said semiconductor structure; 
 a first channel formed between a pair of first regions of a second conductivity type within said substrate for a first MOS transistor which is stacked on a third MOSFET of a second conductivity type; and 
 a second channel formed between a pair of second regions of a second conductivity type within said substrate for a second MOS transistor which is stacked on a fourth MOSFET of a second conductivity type, wherein, wherein a channel length of said first channel is longer than a channel length of said second channel to increase a drain base breakdown voltage of said first MOS transistor; 
 an additionala pick up diffusion region is disposed between the source region of said first regions and the source of said second regions for surroundinghaving a first portion that surrounds said first MOS transistor with an additionalin plan view, and having a second portion that surrounds said second MOS transistor in plan view, wherein the first and second portions of the pick up diffusion toregion have a common part for restrainrestraining the turn on of said first MOS transistor, the common part being disposed between a source region of said first regions and a source of said second regions, wherein part of the first portion of the pick up diffusion region is not part of the second portion of the pick up diffusion region, and wherein part of the second portion of the pick up diffusion region is not part of the first portion of the pick up diffusion region. 
 
     
     
       9. The semiconductor structure of  claim 8 , wherein the channel length of said first channel is longer than the channel length of said second channel to increase the drain base breakdown voltage of said first MOS transistor. 
     
     
       10. An apparatus for electrostatic discharge protection of a metal oxide semiconductor (CMOS) circuit, said apparatus comprising:
 a semiconductor substrate;   a first MOS type transistor disposed on said semiconductor substrate; and   a second MOS type transistor disposed proximate to said first MOS type transistor on said semiconductor substrate, and   a pick up diffusion region having a first portion that laterally surrounds an area including said first MOS transistor and excluding said second MOS transistor, wherein the pick up diffusion region has a second portion that laterally surrounds said second MOS transistor, wherein said first and second portions share a common side of said pick up diffusion region that is disposed between a source of the first MOS type transistor and a source of the second MOS type transistor;   wherein a channel length of said first MOS type transistor is longer than a channel length of said second MOS type transistor such that a drain-base voltage of said first MOS type transistor is increased with respect to a drain-base voltage of said second MOS type transistor.   
     
     
       11. A semiconductor structure for electrostatic discharge (ESD) protection of a metal oxide semiconductor (MOS) integrated circuit, said semiconductor structure comprising:
 a substrate of a first conductivity type that forms a base for said semiconductor structure;   a first region of a second conductivity type within said substrate that forms a drain of a first MOS transistor;   a second region of the second conductivity type within said substrate that forms a source of the first MOS transistor;   means for restraining the turn on of said first MOS transistor, said means for restraining surrounding said first MOS transistor on four sides;   a first channel region disposed between said first and second regions of said first MOS transistor; and   a second channel region disposed adjacent to a third region of a second MOS transistor that forms a source of the second MOS transistor, wherein a first channel length of said first channel region is longer than a channel length of said second channel region to increase a drain-base breakdown voltage of said first MOS transistor;   wherein the means for restraining is disposed between the second region and the third region.