Circuit and method for processing communication packets and valid data bytes

Abstract

Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

What is claimed is: 
     
       1. A method for processing data packets within a communication system comprising:
 receiving a first data packet having a plurality of bytes of data; 
 determining whether the first data packet ends with an invalid byte of data; 
 if an invalid byte of data is detected in the first data packet, dropping the invalid byte of data; 
 receiving a second data packet having a plurality of bytes of data; 
 shifting a byte of data from the second data packet in place of the dropped invalid byte of data in the first data packet; and 
 continuecontinuing shifting data one byte at a time in the second data packet. 
 
     
     
       2. The method of  claim 1  wherein each byte of data in a data packet forms one half of a data word. 
     
     
       3. The method of  claim 2  wherein each data word comprises a first 16-bit byte and a second 16-bit byte, and the communication system is a synchronous optical network (SONET). 
     
     
       4. A method for processing data packets within a communication system, the method comprising:
 receiving a first data packet in the communication system, the first data packet ending with a valid byte and an invalid byte of data; 
 dropping the invalid byte of data; 
 receiving a second data packet that begins with a first valid byte of data; and 
 concatenating the valid byte of the first data packet with the first valid byte of the second data packet. 
 
     
     
       5. The method of  claim 4  wherein the second data packet further comprises a second valid byte, a third valid byte and a fourth invalid byte. 
     
     
       6. The method of  claim 5  further comprising shifting the second valid byte into a location previously occupied by the first valid byte. 
     
     
       7. The method of  claim 6  further comprising shifting the third valid byte into a location previously occupied by the second valid byte. 
     
     
       8. The method of  claim 5  further comprising flagging the fourth invalid byte as invalid. 
     
     
       9. The method of  claim 4  wherein the act of concatenating further comprising comprises concatenating the valid byte of the first data packet and the first valid byte of the second data packet into a 128 bit envelope. 
     
     
       10. The method of  claim 4  wherein the second data packet is 16 bits. 
     
     
       11. The method of  claim 4  wherein the communication system is a synchronous optical network (SONET). 
     
     
       12. The method of  claim 4  wherein the act of concatenating further comprises linking the valid byte of the first data packet and the first valid byte of the second data packet into a high speed packed packet. 
     
     
       13. The method of  claim 12  wherein the high speed packet is 128 bits. 
     
     
       14. The method of  claim 11  wherein concatenating occurs at an interface between a framing chip and a system chip. 
     
     
       15. A concatenation circuitry, comprising:
 a first multiplexing logic circuitry having a data output port, a data select port, and first and second data input ports, the data select port for selectively coupling any one of the first, or second data input ports to the data output port; 
 a first register, having a data input port for receiving input data and a data output port for coupling to the first data input port of the first multiplexing logic circuitry; 
 a second register having a data input port for receiving input data, and for coupling to the data input port of the first register, the second register having a data output port for coupling to the second data input port of the first multiplexing logic circuitry; 
 a third register having a data input port for coupling to the data output port of the first multiplexing logic circuitry, and a data output port for outputting data; 
 a fourth register having a data input port, and a data output port for outputting data; and 
 a second multiplexing logic circuitry having a first data input port for coupling to the data output port of the second register, the second multiplexing logic circuitry having a second data input port for coupling to the data input port of the second first register, the second multiplexing logic circuitry having a data output port for coupling to the data input port of the fourth register, and the second multiplexing logic circuitry having a data select port for selectively coupling either the first data input port or the second data input port with the data output port of the second multiplexing logic circuitry. 
 
     
     
       16. The circuitry of  claim 15  wherein the data output port of the fourth register is for bits  0  through  7 . 
     
     
       17. The circuitry of  claim 15  wherein the data output ort of the third register is for bits  8  through  15 . 
     
     
       18. A logic circuitry for processing data packets within a communication system such that data packets contain valid bytes of data, the circuitry comprising:
 logic circuitry for determining that a first data packet ends with a valid byte and an invalid byte of data; 
 logic circuitry for dropping the invalid byte of data; 
 logic circuitry for determining that a second data packet that begins with a valid byte of data; and 
 logic circuitry for concatenating the valid byte of the first data packet with the valid byte of the second data packet. 
 
     
     
       19. The logic circuitry of  claim 18  further comprising logic circuitry for linking the valid byte of the first data packet and the valid byte of the second data packet into a high speed packed packet. 
     
     
       20. The logic circuitry of  claim 18  wherein the high speed packet is 128 bits. 
     
     
       21. The logic circuitry of  claim 18  wherein the first data packet is 16 bits wide. 
     
     
       22. The logic circuitry of  claim 18  wherein concatenating occurs at an interface between a framing chip and a system chip. 
     
     
       23. A circuit for processing packets of data wherein a packet includes one or more words each having a first byte and a second byte, the circuit comprising:
 a first register coupled to receive and store the first byte of each word; 
 a second register coupled to receive and store the second byte of each word; 
 a third register coupled to the first register and configured to receive and store contents of the first register in response to a clock signal; 
 a fourth register coupled to the second register and configured to receive and store contents of the second register in response to the clock signal; and 
 a multiplexing circuit coupled to the third and fourth registers and configured to selectively rearrange pairing of bytes. 
 
     
     
       24. The circuit of  claim 23  wherein the multiplexing circuit comprises a first multiplexer having a first input coupled to an output of the third register, and having a second input coupled to an output of the fourth register. 
     
     
       25. The circuit of  claim 24  wherein the multiplexing circuit comprises a second multiplexer having a first input coupled to an the output of the fourth register, and having a second input coupled to an input of the third register. 
     
     
       26. The circuit of  claim 25  further comprising control logic circuitry coupled to a select port of the first multiplexer and a select port of the second multiplexer. 
     
     
       27. The method of claim 1 wherein the communication system transmits digital bit streams via repeating fixed frames.  
     
     
       28. The method of claim 4 wherein the communication system transmits digital bit streams via repeating fixed frames.  
     
     
       29. The logic circuitry of claim 18 wherein the communication system transmits digital bit streams via repeating fixed frames.  
     
     
       30. The method of claim 1, wherein the first data packet is received at a framer.  
     
     
       31. The method of claim 1, further comprising:
 sending the first data packet from a network processor.    
     
     
       32. A system, comprising:
 a transmitting communication device configured to transmit a plurality of data packets at a multiple-byte-wide interface, wherein at least one packet in the plurality of data packets comprises one or more invalid bytes; and   a receiving communication device comprising:
 a receiver configured to receive the plurality of data packets, and 
 a shifter utilizing byte shifting to remove the one or more invalid bytes from the at least one packet.  
   
     
     
       33. The system of claim 32, wherein the transmitting communication device is a network processor.  
     
     
       34. The system of claim 32, wherein the receiving communication device is a framer.  
     
     
       35. The system of claim 32, wherein the shifter comprises:
 one or more registers; and   one or more multiplexers.    
     
     
       36. The system of claim 35, wherein the one or more multiplexers provides an output based on a presence of the one or more invalid bytes.  
     
     
       37. The system of claim 36, wherein a first multiplexer of the one or more multiplexers provides an output from a first register of the one or more registers, and provides an output from a second register of the one or more registers upon detection of an invalid byte.  
     
     
       38. The system of claim 32, wherein the shifter stores bytes received from the multiple-byte-wide interface in a plurality of registers, and generates an output by (i) selecting registers to provide the output, and (ii) removing invalid bytes by altering the selection of registers.  
     
     
       39. The system of claim 32, further comprising:
 a serializer-deserializer configured to accept an output of the receiving communication device.    
     
     
       40. The system of claim 39, wherein the output of the receiving communication device comprises an output of a first multiplexer.  
     
     
       41. The system of claim 39, wherein the output of the receiving communication device is null in a presence of two or more invalid bytes.  
     
     
       42. The system of claim 41, wherein the receiving communication device further comprises a clock and wherein the output of the receiving communication device is null for at least one cycle of the clock in the presence of two or more invalid bytes.  
     
     
       43. A framer, configured for use in a communication system, comprising:
 a receiver configured to receive a plurality of packets, wherein at least one packet in the plurality of packets comprises one or more invalid bytes; and   a shifter utilizing byte shifting to remove the one or more invalid bytes from the at least one packet in the plurality of packets; and   a transmitter configured to send one or more packets in the plurality of packets in a fixed frame, wherein each of the sent one or more packets has the one or more invalid bytes removed.    
     
     
       44. The logic circuitry of claim 42, wherein the communication system transmits digital bit streams via repeating fixed frames.  
     
     
       45. A method for processing data packets comprising:
 receiving a first data packet having a plurality of bytes of data;   determining whether the first data packet ends with an invalid byte of data;   if an invalid byte of data is detected in the first data packet, dropping the invalid byte of data;   receiving a second data packet having a plurality of bytes of data;   shifting a byte of data from the second data packet in place of the dropped invalid byte of data in the first packet; and   continuing to shift data one byte at a time from the second data packet.    
     
     
       46. The method of claim 45, wherein the data packets are processed within a communication system, and the communication system transmits digital bit streams via repeating fixed frames.