Dynamic memory management

Abstract

In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power needed to maintain information, and a threshold for determining when to power down a battery powered device are used to maximize battery life.

What is claimed is: 
     
       1. A device comprising:
 a synchronous dynamic memory;   a clock signal supplied externally to the dynamic memory;   wherein the dynamic memory is refreshed at a determined minimum refresh rate to avoid loss of its stored information;   wherein the dynamic memory is adapted to undergo read, write, and refresh cycles responsively to the clock signal; and   wherein the clock signal to the dynamic memory, in power up mode, only when needed for a read, write, or refresh of the dynamic memory.   
     
     
       2. A device comprising:
 a plurality of synchronous dynamic memories, wherein each dynamic memory is refreshed at a determined minimum refresh rate to avoid loss of associated stored information, and wherein each dynamic memory is adapted to be used in one of at least two device modes, the device modes including (a) power up mode and (b) power down mode, and wherein each dynamic memory is further adapted to receive a clock signal from an external source; and 
 a controller configured to refresh each dynamic memory at a determined minimum refresh rate that is lower than a self-refresh rate of the plurality of synchronous dynamic memories; 
 and a clock signal supplied externally to the dynamic memories; 
 wherein each dynamic memory is adapted to undergo read, write, and refresh cycles responsively to the clock signal; 
 wherein one of the dynamic memories undergoing is configured to undergo a read or write cycle is when in the power up mode; 
 wherein information is allocated among the dynamic memories to predispose the storage of related information on one of the dynamic memories; 
 wherein the clock circuitry is configured to supply the clock signal is supplied to the dynamic memories only when needed for a read or a write, and at least at the determined refresh rate of the dynamic memories; and 
 whereby other dynamic memories are configured to be in the power down mode while said one of the dynamic memories is in the power up mode. 
 
     
     
       3. A device comprising:
 a processor;   a plurality of synchronous dynamic memories;   a clock signal supplied externally to the dynamic memories;   wherein each dynamic memory is adapted to store information;   wherein each dynamic memory is refreshed at a determined minimum refresh rate to avoid loss of its stored information;   wherein each dynamic memory is adapted to be used in one of at least two device modes, the device modes including (a) power up mode and (b) power down mode;   wherein each dynamic memory is adapted to undergo read, write, and refresh cycles responsively to the clock signal;   wherein one of the dynamic memories undergoing a read or write cycle is in the power up mode;   wherein the processor allocates storage of information among the dynamic memories to create a tendency for related information to be stored on the said one of the dynamic memories to the extent possible, whereby other dynamic memories are in the power down mode while said one of the dynamic memories is in the power up mode;   wherein the clock signal is supplied to the dynamic memories only when needed for a read or a write, and at the minimum refresh rate of the dynamic memories;   and wherein the processor determines the minimum refresh rate for each dynamic memory.   
     
     
       4. The device according to  claim 3  claim 2, further comprising:
 a computing device including a secondary memory; 
 wherein each dynamic memory is adapted to be in communication with the secondary memory; 
 such that the stored information of each dynamic memory can be backed up on the secondary memory; and 
 such that backed up information on the secondary memory can be restored from the secondary memory. 
 
     
     
       5. The device according to  claim 3  claim 2, wherein a constant voltage is supplied to each dynamic memory. 
     
     
       6. The device according to  claim 3  claim 2, further comprising:
 a refresh circuit; 
 wherein the refresh circuit generates a square wave; and 
 wherein, when the dynamic memory is used in a device power down mode, the clock signal is responsive to the refresh circuit's square wave. 
 
     
     
       7. The device according to  claim 6 , further comprising:
 resistor pull-ups; 
 resister pull-downs; and 
 wherein the resistor pull-ups and resistor pull-downs are configured to enable the dynamic memory to undergo refresh cycles while the remainder of the device is in a powered down mode. 
 
     
     
       8. The device according to  claim 3  claim 2, further comprising:
 a first battery; 
 a second battery; 
 wherein the first battery is adapted to provide sufficient power to enable each of the plurality of dynamic memories to undergo refresh cycles; 
 wherein the second battery is adapted to provide sufficient power to enable each of the plurality of dynamic memories to undergo refresh cycles; and 
 wherein loss of the stored information of each of the plurality of dynamic memories is avoided so long as at least one of the batteries is sufficiently charged and engaged. 
 
     
     
       9. The device according to  claim 3  claim 2, further comprising:
 a battery; 
 wherein the battery is adapted to provide, when sufficiently charged and engaged, sufficient power to enable each of the plurality of dynamic memories to undergo refresh cycles; 
 wherein the battery is adapted to be recharged to be at least sufficiently charged; and 
 whereby loss of the stored information of each of the dynamic memories is avoided so long as the battery is sufficiently charged and engaged. 
 
     
     
       10. The device according to  claim 9 ,
 wherein a charge threshold is at least sufficient that the battery charged at the charge threshold would be sufficiently charged; 
 wherein the battery is adapted to have its charge determined; 
 wherein, if the battery charge is less than the charge threshold, the device is powered down; and 
 wherein the remaining battery charge is utilized to avoid loss of the stored information of the plurality of dynamic memories. 
 
     
     
       11. A method for refreshing a synchronous dynamic memory in a powerup mode, the method comprising:
 executing a read cycle on the dynamic memory responsively to receiving a read instruction and a clock signal; 
 executing a write cycle on the dynamic memory responsively to receiving a write instruction and the clock signal; 
 executing a refresh cycle, at a determined minimum refresh rate thereby refreshing to refresh the dynamic memory, responsively wherein the determined minimum refresh rate is less than a self-refresh rate of the synchronous dynamic memory, wherein said executing is responsive to receiving the clock signal, not receiving a read instruction, and not receiving a write instruction; and 
 actuating the clock signal only when executing a read, write or refresh cycle, and such that the dynamic memory does not lose its stored information. 
 
     
     
       12. A device comprising:
 a synchronous dynamic memory;   a clock signal supplied externally to the dynamic memory;   wherein the dynamic memory is refreshed at a determined minimum refresh rate to avoid loss of its stored information;   wherein the dynamic memory is adapted to undergo refresh cycles responsively to the clock signal; and   wherein the clock signal is supplied to the dynamic memory, in a power-down mode, at least at the determined minimum refresh rate.   
     
     
       13. A method for refreshing a synchronous dynamic memory in a power-down mode, the method comprising:
 determining a minimum refresh rate at which the dynamic memory must be refreshed at to avoid loss of its stored information, wherein the minimum refresh rate is less than a self-refresh rate of the synchronous dynamic memory; 
 supplying a clock signal externally to the dynamic memory at least at the determined minimum refresh rate; and 
 executing a refresh cycle, thereby refreshing the dynamic memory, responsively to receiving the clock signal. 
 
     
     
       14. An apparatus, comprising:
 a memory requiring refresh operations to prevent loss of stored data;   a power source configured to provide power for the refresh operations and access operations of the memory; and   a controller external from and coupled to the memory and that is configured to:
 periodically issue refresh commands to refresh the memory at a determined minimum refresh rate, wherein the determined minimum refresh rate is lower than a self-refresh rate of the memory, and wherein the determined minimum refresh rate is selected to prevent loss of data, 
 issue non-periodic access commands to the memory, and 
 issue clock signals to the memory only along with the periodic refresh commands and the non-periodic access commands. 
   
     
     
       15. The apparatus of claim 14, further comprising a refresh circuit configured to issue refresh signals to the memory at the refresh rate, and wherein the controller is further configured to detect a low-power level condition of the power source and to activate the refresh circuit in response to the low-power level condition. 
     
     
       16. The apparatus of claim 15, wherein the memory is a synchronous dynamic random access memory (SDRAM) configured to operate in an auto-refresh mode, and wherein the refresh signals are clock signals. 
     
     
       17. The apparatus of claim 16, further comprising resistor pin straps coupled to pins of the SDRAM, and wherein the controller is configured to set the resistor pin straps to configure the SDRAM for the auto-refresh mode. 
     
     
       18. The apparatus of claim 15, wherein the controller is further configured to reserve power to the refresh circuit and to the memory in response to the low-power level condition to maintain the stored data. 
     
     
       19. The apparatus of claim 18, wherein the memory comprises multiple memory chips, and wherein the controller is further configured to:
 receive data to be written to the memory; and   write the received data to as few of the memory chips as necessary to store the received data.   
     
     
       20. The apparatus of claim 14, wherein the memory comprises multiple memory chips, and wherein the controller is further configured to:
 place at least one of the memory chips into an inactive state requiring a reduced power level compared to an active state; and   maintain at least another one of the remaining memory chips in the active state.   
     
     
       21. The apparatus of claim 14, wherein the power source comprises a battery. 
     
     
       22. The apparatus of claim 14, wherein the power source comprises two batteries, wherein both batteries are independently sufficient to power the memory to maintain the stored data. 
     
     
       23. A method, comprising:
 powering, by one or more batteries, a synchronous dynamic random access memory (SDRAM) of an apparatus;   issuing, by a controller that is external to the SDRAM, non-periodic access commands to the SDRAM;   periodically issuing, by the controller, refresh commands to periodically refresh the SDRAM at a determining minimum refresh rate that is lower than a self-refresh-mode refresh rate of the SDRAM; and   only issuing, by the controller, clock signals with the issued refresh operations and issued access commands.   
     
     
       24. The method of claim 23, further comprising:
 determining, by the controller, that an available power level of the one or more batteries is lower than a pre-determined minimum power level;   in response to said determining, activating by the controller a refresh circuit to issue periodic clock signals at the reduced refresh rate to maintain data stored on the SDRAM; and   in response to said determining, disabling, by the controller, all components of the apparatus other than the SDRAM and the refresh circuit.   
     
     
       25. The method of claim 23, wherein the SDRAM further comprises multiple SDRAM chips, wherein the method further comprises placing, by the controller, at least one of the SDRAM chips into an inactive mode requiring less power than an active mode and maintaining at least one other SDRAM chip in the active mode. 
     
     
       26. The method of claim 23, wherein the access commands comprise at least one write command to write received data to the SDRAM, wherein the SDRAM comprises a plurality of SDRAM chips, and wherein the method further comprises determining relatedness of the received data and writing related data to one of the plurality of the SDRAM chips.