Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

Abstract

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

What is claimed is: 
     
       1. A multi-block display-refresh controller comprising:
 a start address selector for selecting a block starting address from a plurality of block starting addresses and a screen starting address, the start address selector being loaded with a series of block starting addresses for a plurality of blocks within a display frame;   a selector, coupled to the start address selector, for selecting either the block starting address or a next-line address for output;   a line start register, coupled to receive an output of the selector, for storing a line starting address for a horizontal line of pixels in the display frame;   a memory address counter that is loaded with the line starting address from the line start register and incremented by a pixel clock as pixels in the horizontal line are written to a display;   an adder, receiving the line starting address from the line start register, for adding a line width to the line starting address to generate the next-line address to the selector;   a block-end detector, coupled to receive a pixel address from the memory address counter, for detecting a block end when the pixel address matches a block-end address for a current one of the plurality of blocks within the display frame; and   wherein the selector selects a new block starting address from the start address selector when the block-end detector detects the block end, but the selector selects the next-line address from the adder when the block end is not detected by the block-end detector,   whereby new block starting address are used when block ends are detected as the plurality of blocks of pixels are displayed within a display frame.   
     
     
       2. The multi-block display-refresh controller of  claim 1  wherein when the block end is detected the line start register is loaded from the selector and the memory address counter is loaded from the line start register using a new block starting address from the start address selector,
 whereby pixel addresses are re-loaded when the block end is detected. 
 
     
     
       3. The multi-block display-refresh controller of  claim 2  wherein the block end can occur in a middle of a horizontal line of pixels, wherein pixels from two blocks are displayed on a same horizontal line, wherein the two blocks are in non-adjacent memory locations separated by other data. 
     
     
       4. The multi-block display-refresh controller of  claim 3  wherein the block end can also occur at an end of the horizontal line;
 further comprising:
 a comparator, receiving the next-line address from the adder, for comparing the next-line address to the block-end address and signaling the block end when the next-line address exceeds the block-end address. 
 
 
     
     
       5. The multi-block display-refresh controller of  claim 4  wherein the start address selector is repeatedly over-written with a new block starting address as the series of blocks of pixels in the display frame are read;
 wherein the block-end address is stored in a block-end register that is repeatedly over-written with a new block-end address for the block that had a block starting address in the start address selector. 
 
     
     
       6. A portable system comprising:
 execute means for executing programs that write pixels for display to a single-block frame buffer;   frame-buffer-address translate means, receiving addresses of pixels from the execute means, for translating the addresses of pixels to memory addresses in a plurality of physical memory blocks;   low-power memory means for storing some of the plurality of physical memory blocks that store pixels;   high-power-memory access means for reading pixels stored in others of the plurality of physical memory blocks that are stored in an external memory;   wherein accesses of pixels stored in the external memory consume more power than accesses of pixels stored in the low-power memory means; and   display controller means for writing pixels to a display, the display controller means reading pixels stored in the plurality of physical memory blocks including reading pixels stored in the low-power memory means and pixels stored in the external memory;   wherein the display controller means further comprises:
 pixel counter means, having a pixel address that is incremented in response to a pixel clock as pixels are read from the lower-power memory means or from the external memory; 
 block-end register means for storing a block-end address of a current block in the plurality of physical memory blocks; 
 block-start register means for storing a block-start address of the current block in the plurality of physical memory blocks; 
 block-end detect means for detecting a block end when the pixel address from the pixel counter means reaches the block-end address from the block-end register means; 
 select means for loading the pixel counter means with a next block-start address from the block-start register means when the block-end detect means detects the block end, 
 line start register means, loaded by the select means with the next block-start address when the block end is detected, for storing a starting pixel address for a display line; and 
 add means, receiving the starting pixel address from the line start register means, for adding a line-width of pixels to generate a next-line starting pixel address to be loaded into the line start register means at an end of the display line; 
   
       whereby pixels in the single-block frame buffer are stored in multiple physical blocks in both the low-power memory means and in the external memory and whereby the pixel counter means is re-loaded with the next block-start address when the block end is detected. 
     
     
       7. The portable system of  claim 6  wherein the low-power memory means is a memory on a same substrate as the execute means and the display controller means, but the external memory is on a separate substrate. 
     
     
       8. The portable system of  claim 6  wherein the display controller means can enter a low-power mode wherein pixels are fetched only from the low-power memory means but not from the external memory, the display controller means can also enter a high-power mode wherein pixels are fetched from both the low-power memory means and from the external memory;
 wherein the high-power mode consumes more power that the low-power mode. 
 
     
     
       9. The portable system of  claim 6  further comprising:
 window means, in the display controller means, for detecting when a current location for pixel fetching reaches a window limit, the window means preventing memory accesses to fetch pixels after the window limit is reached but instead supplying a fixed pixel for display, 
 whereby fixed pixels rather than memory-fetched pixels are displayed once the window limit is reached. 
 
     
     
       10. An integrated circuit capable of being coupled, during use, to an external memory that is separate from the integrated circuit, the integrated circuit comprising:
 a memory configured to store a first memory block of a frame buffer that comprises a plurality of memory blocks in a full power mode, wherein at least one of the other memory blocks of the plurality of memory blocks are stored in the external memory in the full power mode; and   a display controller coupled to the memory and configured to read pixels from the memory to be displayed on a display screen, and wherein, in a low power mode, the display controller is configured to display pixels read from the frame buffer on a reduced window of the display screen that excludes a portion of the display screen, and wherein the display controller is configured to read the displayed pixels for the reduced window only from the first memory block in the memory, and wherein the display controller is configured to display a fixed pixel not read from the memory or the external memory for the remaining pixels on the display screen outside of the reduced window, and wherein, in the full power mode, the display controller is configured to read pixels to be displayed from both the memory and the external memory.   
     
     
       11. The apparatus as recited in claim 10 wherein the display controller comprises a pixel counter configured to count a number of pixels from a current display line that have been displayed, and wherein the display controller is configured to fetch pixels from the memory for display until the counter reaches an end of the reduced window, and wherein the display controller is configured to display the fixed pixel for the remainder of the current display line. 
     
     
       12. The apparatus as recited in claim 11 wherein the remainder of the current display line is mapped to addresses in the memory, but the display controller is configured to display the fixed pixel responsive to the counter reaching the end of the reduced window. 
     
     
       13. The apparatus as recited in claim 12 wherein the display controller is configured to not fetch the pixels corresponding to the remainder of the current display line from the memory. 
     
     
       14. The apparatus as recited in claim 10 wherein the display controller comprises a line counter configured to indicate a line number of the current display line, and wherein the display controller is configured to display only the fixed pixel for remaining display lines when the line number reaches an end of the reduced window. 
     
     
       15. The apparatus as recited in claim 14 wherein pixels from one or more of the remaining display lines are mapped to addresses in the memory, but the display controller is configured to display the fixed pixel responsive to the counter reaching the end of the reduced window. 
     
     
       16. The apparatus as recited in claim 15 wherein the display controller is configured to not fetch the pixels corresponding to the remaining display lines from the memory. 
     
     
       17. A method comprising:
 in a low power mode, displaying pixels read from a frame buffer on a reduced window of a display screen that excludes a portion of the display screen, wherein the displaying comprises:
 reading the displayed pixels for the reduced window only from a first block in a memory included on a same integrated circuit as a display controller that performs the displaying; and 
 displaying a fixed pixel not read from the memory or the external memory for the remaining pixels on the display screen outside of the reduced window; and 
   in a full power mode, displaying pixels read from both the memory and an external memory coupled to the integrated circuit.   
     
     
       18. The method as recited in claim 17 further comprising, in the low power mode, displaying a different image on the reduced window than is displayed on a full window that includes the frame buffer data from the memory and from the external memory. 
     
     
       19. The method as recited in claim 18 wherein the different image comprises status data for a device that includes the integrated circuit. 
     
     
       20. The method as recited in claim 18 wherein the different image comprises a smaller amount of information than is displayed in a full power mode. 
     
     
       21. The method as recited in claim 17 further comprising:
 detecting that pixels displayed from the current display line have reached an end of the reduced window;   ceasing fetching pixels from the memory for display responsive to the detecting; and   displaying the fixed pixel for the remainder of the current display line.   
     
     
       22. The method as recited in claim 21 wherein the remainder of the current display line is mapped to addresses in the memory, but the fixed pixel is displayed. 
     
     
       23. The method as recited in claim 17 further comprising:
 detecting that the current display line is an end of the reduced window;   ceasing fetching pixels from the memory for display responsive to the detecting; and   displaying the fixed pixel for the remaining display lines.   
     
     
       24. The method as recited in claim 23 wherein pixels from one or more of the remaining display lines are mapped to addresses in the memory, but the fixed pixel is displayed. 
     
     
       25. A portable device comprising:
 a display screen; and   an integrated circuit coupled to the display screen, wherein the integrated circuit comprises:
 a memory configured to store a first memory block of a frame buffer that comprises a plurality of memory blocks in a full power mode, wherein at least one of the other memory blocks of the plurality of memory blocks are stored in an external memory separate from the integrated circuit in the full power mode; and 
 a display controller coupled to the memory and configured to read pixels from the memory to be displayed on a display screen, and wherein, in a low power mode, the display controller is configured to display pixels read from the frame buffer on a reduced window of the display screen that excludes a portion of the display screen, and wherein the display controller is configured to read the displayed pixels for the reduced window only from the first memory block in the memory, and wherein the display controller is configured to display a fixed pixel not read from the memory or the external memory for the remaining pixels on the display screen outside of the reduced window, and wherein, in the full power mode, the display controller is configured to read pixels to be displayed from both the memory and the external memory. 
   
     
     
       26. The portable device as recited in claim 25 wherein the portable device is a portable communication device. 
     
     
       27. The portable device as recited in claim 25 wherein the portable device is a portable computing device. 
     
     
       28. The portable device as recited in claim 25 further comprising the external memory coupled to the integrated circuit.