Automatic circuit and method for temperature compensation of oscillator frequency variation over temperature for a real time clock chip

Abstract

An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.

We claim: 
     
       1. An automatic temperature compensated real-time clock (RTC) chip, comprising:
 a clock portion including a crystal oscillator block comprising crystal compensation circuitry adapted to be coupled to a crystal, said crystal compensation circuitry comprising a non-linear capacitor DAC including a plurality of load capacitors, said load capacitors having respective switches which switch respective ones of said load capacitors to change a parallel resonance frequency (fp) generated by said oscillator block, wherein said capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of said switches to provide a non-linear change in overall load capacitance to result in a linear relationship between said fp and said ATR bits; 
 a temperature sensor block coupled to said crystal for measuring a temperature of at least said crystal; 
 an A/D converter coupled to said temperature sensor for outputting a digital temperature signal representative of said temperature of said crystal, and 
 a DSP engine for receiving said digital temperature signal, said DSP engine calculating frequency correction needed to correct for frequency inaccuracy and determining a bit sequence comprising said ATR bits to achieve said frequency correction. 
 
     
     
       2. The RTC of  claim 1 , wherein said non-linear DAC comprises a piecewise linear segmented DAC, comprising a plurality of piecewise linear segments connected in parallel. 
     
     
       3. The RTC of  claim 2 , wherein said plurality of segments are binary weighted segments. 
     
     
       4. The RTC of  claim 2 , wherein some of said plurality of segments are controlled by a first number of said ATR bits and other of said plurality of segments are controlled by a different number of said ATR bits. 
     
     
       5. The RTC of  claim 1 , further comprising thermometer decoder logic for receiving said ATR bits and generating a plurality of control lines for controlling said switches. 
     
     
       6. The RTC of  claim 1 , wherein said DSP calculation splits said frequency correction into said ATR bits and into coarser Digital Trimming (DTR) bits, wherein said digital trimming bits are operable to perform frequency correction by adding or skipping clock cycles. 
     
     
       7. The RTC of  claim 6 , further comprising a RTC digital trimming module including a clock divider chain for generating a 1 Hz clock from said fp, wherein said DTR bits are coupled to an input of said digital trimming module, wherein said digital trimming module performs said frequency adjustment on said 1 Hz clock. 
     
     
       8. The RTC of  claim 1 , wherein said temperature sensor block comprises a delta Vbe-based temperature sensor. 
     
     
       9. The RTC of  claim 8 , wherein said temperature sensor block further comprises a PTAT block coupled between said Vbe-based temperature sensor and said A/D converter, wherein process trim (PTR) bits coupled to said PTAT trim at least one of offset and gain for said A/D converter. 
     
     
       10. The RTC of  claim 1 , wherein said chip runs at an average current of <1 μA and an average power of <5 μW. 
     
     
       11. The RTC of  claim 10 , further comprising a buck voltage regulator on said chip for stepping down a supply voltage received by said chip to a lower level. 
     
     
       12. The RTC of  claim 1 , wherein said temperature sensor block operates with a duty cycle of <1:1,000. 
     
     
       13. The RTC of  claim 7 , wherein said DSP engine is configured exclusive of hardware multipliers. 
     
     
       14. The RTC of  claim 7 , wherein said A/D converter is a switched-capacitor based A/D converter. 
     
     
       15. A method for temperature compensating a real time clock (RTC) circuit, comprising the steps of:
 providing a real-time clock (RTC) having a crystal oscillator block comprising a crystal coupled to crystal compensation circuitry, said crystal compensation circuitry comprising a non-linear Capacitor DAC having a plurality of load capacitors having respective switches which switch respective ones of said load capacitors to change a parallel resonance frequency (fp) generated by said oscillator block, wherein said capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of said switches to provide a non-linear change in overall load capacitance resulting in a linear relationship between said fp and said ATR bits; 
 measuring a temperature of said crystal; 
 generating an input code comprising said ATR bits based on said temperature to correct said fp, and 
 frequency correcting by applying said input code as said input code vectors to said Capacitor DAC to provide a frequency shift to temperature correct an oscillator frequency of said crystal oscillator. 
 
     
     
       16. The method of  claim 15 , wherein said linear relationship comprises a constant integer/bit. 
     
     
       17. The method of  claim 15 , wherein said generating comprises generating Digital Trimming (DTR) in addition to said ATR bits, wherein said DTR bits provide a coarser frequency adjustment as compared to said ATR bits and are operable by adding or skipping clock cycles derived from said oscillation frequency. 
     
     
       18. The method of  claim 17 , wherein a trim frequency resolution of an LSB of said DTR bits is more than a maximum trim frequency adjustment provided by said ATR bits. 
     
     
       19. The method of  claim 15 , wherein said RTC runs at an average current of <1 μA and an average power of <5 μW. 
     
     
       20. The method of  claim 15 , wherein said frequency correcting comprises continuous non-overlapping frequency adjustment over a range of at least 100 ppm. 
     
     
       21. An automatic temperature compensated real-time clock (RTC) chip, comprising:
 a clock portion including a crystal oscillator block comprising crystal compensation circuitry adapted to be coupled to a crystal, said crystal compensation circuitry comprising a non-linear capacitor DAC, wherein said non-linear capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause a non-linear change in overall load capacitance to result in a linear relationship between said ATR bits and a parallel resonance frequency (fp) generated by said oscillator block;   a temperature sensor block coupled to said crystal for measuring a temperature of at least said crystal;   an A/D converter coupled to said temperature sensor for outputting a digital temperature signal representative of said temperature of said crystal, and   a DSP engine for receiving said digital temperature signal, said DSP engine calculating frequency correction needed to correct for frequency inaccuracy and determining a bit sequence comprising said ATR bits to achieve said frequency correction.   
     
     
       22. A method for temperature compensating a real time clock (RTC) circuit, the method comprising:
 measuring a temperature of a crystal oscillator block;   generating an input code comprising Analog Trimming (ATR) bits based on said temperature to correct a parallel resonance frequency (fp) generated by said oscillator block, and   applying said input code as input code vectors to a capacitor DAC to provide a frequency shift to temperature correct an oscillator frequency of said crystal oscillator, wherein said capacitor DAC is arranged so that said ATR bits received cause a non-linear change in overall load capacitance resulting in a linear relationship between said fp and said ATR bits.   
     
     
       23. The RTC chip of claim 21, wherein the bit sequence further comprises Digital Trimming (DTR) bits for coarser frequency correction than the ATR bits. 
     
     
       24. The RTC chip of claim 21, further comprising at least an initial trim register for compensating for an initial frequency error of the crystal. 
     
     
       25. The RTC chip of claim 21, wherein the crystal compensation circuitry digitally trims the parallel resonance frequency by adding or omitting pulses from the clock signal using Digital Trimming (DTR) bits in conjunction with using the bit sequence comprising ATR bits in a continuous and non-overlapping manner. 
     
     
       26. The RTC chip of claim 21, wherein the non-linear capacitor DAC comprises a plurality of piecewise linear segments connected in parallel. 
     
     
       27. The RTC chip of claim 21, wherein the RTC chip is coupled to a computing device, wherein the corrected fp is used to control a calendar of the computing device. 
     
     
       28. The RTC chip of claim 21, wherein each ATR bit corresponds to a 1 ppm frequency shift of the fp. 
     
     
       29. The RTC chip of claim 21, wherein the DSP engine calculating frequency correction is based on a stored relationship of frequency deflection with temperature for the crystal. 
     
     
       30. The method of claim 22, wherein generating an input code further comprises generating Digital Trimming (DTR) bits to correct the parallel resonance frequency, wherein each DTR bit provides a coarser correction to the parallel resonance frequency than an ATR bit. 
     
     
       31. The method of claim 22, further comprising adjusting a calendar of a computing device coupled to the RTC circuit based on the input code. 
     
     
       32. The method of claim 22, wherein generating an input code further comprises using a relationship of frequency deflection with temperature for the crystal oscillator. 
     
     
       33. The method of claim 22, further comprising compensating for an initial freiuency error of the crystal oscillator by storing an initial ATR or Digital Trimming (DTR) bit in at least an initial trim register for compensating for an initial frequency error of the crystal oscillator. 
     
     
       34. The method of claim 33, wherein storing the initial ATR or DTR bit comprises adjusting to correct for aging of the crystal oscillator. 
     
     
       35. The method of claim 34, further comprising:
 providing the temperature corrected oscillator frequency to one of a network device, clock synthesizer, phase lock loop, computing device, or electronic device coupled to the RTC circuit.