Semiconductor device and manufacturing method thereof

Abstract

There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

1. A semiconductor device comprising:
 a first metal wiring buried, via a first barrier metal, in a first wiring groove formed in a first insulating layer formed on a semiconductor substrate; 
 a second insulating layer formed on the first metal wiring; 
 a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer to be electrically connected to the first metal wiring; 
 a third insulating layer formed on the second insulating layer in which the via plug is buried; and 
 a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness different from that of the second barrier metal to be electrically connected to via plug, 
 wherein layer thickness of the second barrier metal is greater than that of the third barrier metal. 
 
     
     
       2. A semiconductor device according to  claim 1 , wherein layer thickness of the second barrier metal is greater than that of the third barrier metal. 
     
     
       3. A semiconductor device according to  claim 1 , wherein the via plug and second metal wiring are formed in separate steps by a single-damascene process. 
     
     
       4. A semiconductor device according to  claim 2 , wherein the via plug and second metal wiring are formed in separate steps by a single-damascene process. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the via plug and second metal wiring are formed in the same step by a dual-damascene process. 
     
     
       6. The semiconductor device according to  claim 2 , wherein the via plug and second metal wiring are formed in the same step by a dual-damascene process. 
     
     
       7. A semiconductor device comprising:
 a first metal wiring buried, via a first barrier metal, in a first wiring groove formed in a first insulating layer formed on a semiconductor substrate; 
 a second insulating layer formed on the first metal wiring; 
 a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer to be electrically connected to the first metal wiring; 
 a third insulating layer formed on the second insulating layer in which the via plug is buried; and 
 a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal including a material different from that of the second barrier metal to be electrically connected to the second metal wiring, 
 wherein the layer thickness of the second barrier metal is greater than that of the third barrier metal. 
 
     
     
       8. A semiconductor device according to  claim 7 , wherein the second barrier metal is a Ti/TiN laminate layer, and the third barrier metal is a Ta layer. 
     
     
       9. The semiconductor device according to  claim 7 , wherein the via plug and second metal wiring are formed in separate steps by a single-damascene process. 
     
     
       10. The semiconductor device according to  claim 8 , wherein the via plug and second metal wiring are formed in separate steps by a single-damascene process. 
     
     
       11. The semiconductor device according to  claim 7 , wherein the via plug and second metal wiring are formed in the same step by a dual-damascene process. 
     
     
       12. The semiconductor device according to  claim 8 , wherein the via plug and second metal wiring are formed in the same step by a dual-damascene process. 
     
     
       13. The semiconductor device according to any one of  claims 7 , wherein the layer thickness of the second barrier metal is greater than that of the third barrier metal. 
     
     
       14. The semiconductor device according to  claim 7 , wherein the second barrier metal has a laminate layer structure. 
     
     
       15. The semiconductor device according to  claim 14 , wherein the laminate layer structure has a great deoxidation function. 
     
     
       16. A semiconductor device comprising:
 a first metal wiring buried, via a first barrier metal, in a first wiring groove formed in a first insulating layer formed on a semiconductor substrate; 
 a second insulating layer formed on the first metal wiring; 
 a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer to be electrically connected to the first metal wiring; 
 a third insulating layer formed on the second insulating layer in which the via plug is buried; and 
 a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal which is formed into a layer in a process different from that of the second barrier metal to be electrically connected to the via plug, 
 wherein the layer thickness of the second barrier metal is greater than that of the third barrier metal. 
 
     
     
       17. A semiconductor device according to  claim 16 , wherein the second barrier metal is formed into the layer by a CVD process, and the third barrier metal is formed into the layer by a sputter process. 
     
     
       18. The semiconductor device according to  claim 16 , wherein the via plug and second metal wiring are formed in separate steps by a single-damascene process. 
     
     
       19. The semiconductor device according to  claim 17 , wherein the via plug and second metal wiring are formed in separate steps by a single-damascene process. 
     
     
       20. The semiconductor device according to  claim 16 , wherein the via plug and second metal wiring are formed in the same step by a dual-damascene process. 
     
     
       21. The semiconductor device according to  claim 17 , wherein the via plug and second metal wiring are formed in the same step by a dual-damascene process. 
     
     
       22. The semiconductor device according to any one of  claims 16 , wherein the layer thickness or material of the second barrier metal is different from that of the third barrier metal. 
     
     
       23. A semiconductor device, comprising:
 a first insulating layer;   a first groove formed in said first insulating layer;   a first barrier metal layer formed in said first groove;   a first metal wiring layer formed in said first groove on said first barrier metal layer;   a second insulating layer formed on said first insulating layer;   a third insulating layer disposed on said second insulating layer;   a second groove for a via hole formed in said second insulating layer exposed to an upper surface of said first metal wiring layer;   a third groove for a second wiring layer formed in said third insulating layer exposed to said second groove;   a second barrier metal layer formed on sidewalls of said second groove and on said upper surface of said first metal wiring layer; and   a third barrier metal layer formed on sidewalls of said third groove and in said second groove on said second barrier metal layer;   the second metal wiring layer formed in said via hole and in said third groove on said third barrier metal layer to provide a via plug, wherein said via plug is electrically connected to said first metal wiring layer; and   said third barrier metal layer formed on sidewalls of said third groove being thinner than a sum of said second barrier metal layer and said third barrier metal layer formed in said second groove.   
     
     
       24. The semiconductor device according to claim 23, wherein said first, second and third barrier metal layers are formed of the same material. 
     
     
       25. The semiconductor device according to claim 23, wherein said material comprises Ta. 
     
     
       26. The semiconductor device according to claim 23, wherein each of said first and second insulating layers comprises a first film formed on a second film, said first film having a dielectric constant higher than that of said second film. 
     
     
       27. The semiconductor device according to claim 23, wherein said first and second metal wiring layers comprise the same material. 
     
     
       28. The semiconductor device according to claim 23, wherein:
 said second barrier metal layer comprises a CVD barrier metal layer; and   said third barrier metal layer comprises a sputtered barrier metal layer.   
     
     
       29. The semiconductor device according to claim 23, wherein each of said first and second insulating layers comprises a low dielectric constant material. 
     
     
       30. The semiconductor device according to claim 23, wherein said second insulating layer comprises a low dielectric constant material formed on a layer having Si and one of N and C. 
     
     
       31. The semiconductor device according to claim 23, wherein each of said first and second insulating layers comprises a layer having Si and one of O and C formed on a low dielectric constant material. 
     
     
       32. The semiconductor device according to claim 23, wherein:
 said second barrier metal layer comprises a Ta layer about 15 nm thick; and   said third barrier metal layer comprises a Ta layer about 5 nm thick.   
     
     
       33. The semiconductor device according to claim 23, wherein each of said first, second and third insulating layers comprises a low dielectric constant film. 
     
     
       34. A semiconductor device, comprising:
 a first insulating layer;   a first groove formed in said first insulating layer;   a first barrier metal layer formed in said first groove;   a first metal wiring layer formed in said first groove on said first barrier metal layer;   a second insulating layer formed on said first insulating layer;   a third insulating layer disposed on said second insulating layer;   a second groove for a via hole formed in said second insulating layer exposed to an upper surface of said first metal wiring layer;   a third groove for a second wiring layer formed in said third insulating layer exposed to said second groove;   a second barrier metal layer formed on sidewalls of said second groove and on said upper surface of said first metal wiring layer;   a third barrier metal layer formed on said second barrier metal layer;   a fourth barrier metal layer formed on sidewalls of said third groove and in said via hole on said third barrier metal layer, and   a second metal wiring layer formed in said via hole and in said third groove on said third barrier metal layer to provide a via plug, wherein said via plug is electrically connected to said first metal wiring layer.   
     
     
       35. The semiconductor device according to claim 34, comprising:
 said fourth barrier metal layer being formed on sidewalls of said third groove and being thinner than a sum of said second barrier metal layer, said third barrier metal layer and said fourth barrier metal layer formed in said second groove.   
     
     
       36. The semiconductor device according to claim 34, wherein:
 said first barrier metal layer comprises Ta;   said second barrier metal layer comprises Ti,   said third barrier metal layer comprises TiN; and   said fourth barrier metal layer comprises Ta.   
     
     
       37. The semiconductor device according to claim 34, wherein each of said first and second insulating layers comprises a first film formed on a second film, said first film having a dielectric constant higher than that of said second film. 
     
     
       38. The semiconductor device according to claim 34, wherein said first and second metal wiring layers comprise the same material. 
     
     
       39. The semiconductor device according to claim 34, wherein each of said first and second insulating layers comprises a low dielectric constant material. 
     
     
       40. The semiconductor device according to claim 34, wherein said second insulating layer comprises a low dielectric constant material formed on a layer having Si and one of N and C. 
     
     
       41. The semiconductor device according to claim 34, wherein each of said first and second insulating layers comprises a layer having Si and one of O and C formed on a low dielectric constant material. 
     
     
       42. The semiconductor device according to claim 34, wherein:
 said second barrier metal layer comprises a Ti layer about 10 nm thick;   said third barrier metal layer comprises a TiN layer about 10 nm thick; and   said fourth barrier metal layer comprises a Ta layer about 5 nm thick.   
     
     
       43. The semiconductor device according to claim 34, wherein each of said first, second and third insulating layers comprises a low dielectric constant film. 
     
     
       44. A semiconductor device comprising
 a first metal wiring buried, via a first barrier metal, in a first wiring groove formed in a first insulating layer formed on a semiconductor substrate;   a second insulating layer formed on the first metal wiring;   a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer to be electrically connected to the first metal wiring;   a third insulating layer formed on the second insulating layer in which the via plug is buried; and   a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness different from that of the second barrier metal;   wherein layer thickness of the second barrier metal is greater than that of the third barrier metal, and the via plug and the second metal wiring are formed by a dual-damascene process.   
     
     
       45. The semiconductor device according to claim 44, wherein the second barrier metal is formed on the first metal wiring. 
     
     
       46. The semiconductor device according to claim 45, wherein:
 said second insulating layer comprises a layer having Si and C; and   said second metal wiring is formed on the layer having Si and C.   
     
     
       47. The semiconductor device according to claim 46, wherein:
 said second insulating layer comprises a layer having Si and N formed on the first insulating layer.   
     
     
       48. The semiconductor device according to claim 47, wherein:
 each of said second and third insulating layers comprises a methylpolysiloxane-based layer.   
     
     
       49. The semiconductor device according to claim 47, wherein each of said second and third insulating layers comprises a low dielectric constant film. 
     
     
       50. The semiconductor device according to claim 46, wherein:
 each of said second and third insulating layers comprises a methylpolysiloxane-based layer.   
     
     
       51. The semiconductor device according to claim 46, wherein each of said second and third insulating layers comprises a low dielectric constant film. 
     
     
       52. The semiconductor device according to claim 46, wherein the via plug and the second metal wiring comprise Cu. 
     
     
       53. The semiconductor device according to claim 46, wherein the second barrier metal and the third barrier metal comprise Ta. 
     
     
       54. The semiconductor device according to claim 1, wherein:
 said second insulating layer comprises a layer having Si and C; and   said second metal wiring is formed on the layer having Si and C.   
     
     
       55. The semiconductor device according to claim 54, wherein:
 said second insulating layer comprises a layer having Si and N formed on the first insulating layer.   
     
     
       56. The semiconductor device according to claim 54, wherein:
 said second insulating layer comprises a methylpolysiloxane-based layer.   
     
     
       57. The semiconductor device according to claim 54, wherein the via plug and the second metal wiring comprise Cu. 
     
     
       58. The semiconductor device according to claim 54, wherein the second barrier metal and the third barrier metal comprise Ta.