Tap connections for circuits with leakage suppression capability

Abstract

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

1. A method comprising:
 forming a first plurality of regions in a substrate of a first type; 
 placing metal at a first location for a first power rail to supply a first potential; 
 connecting the metal from the first location to the first plurality of first regions such that the substrate of the first type has the first potential; 
 coupling the first power rail to a third power rail by a first transistor, wherein the third power rail is for connection to a plurality of circuits; 
 coupling the a second power rail to a fourth power rail by a second transistor, wherein the fourth power rail is for connection to the plurality of circuits; 
 forming the plurality of circuits on the substrate; 
 coupling the third power rail to the plurality of circuits; and 
 coupling the fourth power rail to the plurality of circuits. 
 
     
     
       2. The method of  claim 1 , further comprising:
 indicating a second location for a second power rail to supply a second potential; 
 forming a second plurality of regions in a well of a second type; 
 placing metal in the second location; and 
 connecting the metal from the second location to the second plurality of second regions such that the well of the second type has the second potential. 
 
     
     
       3. The method of claim  1  2, wherein indicating further comprises:
 placing a plurality of feed-throughs at predetermined locations on the substrate. 
 
     
     
       4. The method of  claim 1 , wherein forming a first plurality of regions further comprises:
 diffusing the first plurality of regions into the substrate of the first type. 
 
     
     
       5. The method of  claim 1 , wherein the connecting further comprises:
 creating a plurality of metal lines to connect to the first plurality of regions; and 
 creating a plurality of vias for connecting the plurality of metal lines to the first location. 
 
     
     
       6. The method of  claim 1 , further comprising:
 providing a the third power rail for connection to a the plurality of circuits; 
 providing a the fourth power rail for connection to the plurality of circuits; 
 coupling the first power rail to the third power rail by a first transistor; 
 coupling the second power rail to the fourth power rail by a second transistor; and 
 forming the plurality of circuits on the substrate. 
 
     
     
       7. The method of  claim 1 , further comprising:
 coupling the third power rail to the plurality of circuits; and   coupling the fourth power rail to the plurality of circuits.   
     
     
       8. A method comprising:
 indicating a first location for a first power rail to supply a first potential, wherein the first power rail is assigned to a well of a first type; 
 placing a plurality of connections in the well of the first type such that the well has the first potential; 
 indicating a second location for a second power rail to supply a second potential, wherein the second power rail is assigned to a substrate of a second type; 
 placing a second plurality of connections in the substrate of the second type such that the substrate has the second potential; 
 coupling the first power rail to a third power rail by a first transistor, the third power rail being provided for connection to the a plurality of circuits; 
 coupling the second power rail to a fourth power rail by a second transistor, the fourth power rail being provided for connection to the plurality of circuits; and 
 forming the plurality of circuits on the substrate. 
 
     
     
       9. The method of  claim 8 , wherein the placing further comprises:
 diffusing a plurality of regions into the well; 
 etching a plurality of metal lines between the diffused regions and the first location; 
 laying metal upon the first location; and 
 placing a plurality of vias between the plurality of metal lines and the first location. 
 
     
     
       10. The method of  claim 8 , further comprising:
 indicating a second location for a second power rail to supply a second potential;   assigning the second power rail to a substrate of a second type; and   placing a second plurality of connections in the substrate of the second type such that the substrate has the second potential.