Driving circuit electroluminescence cell

Abstract

A driving circuit for an electro-luminescence (EL) cell includes an EL cell, and a supply circuit selectively applying current to the EL cell based on a pixel signal from a data line. A control circuit controls current flow from the supplying circuit to the EL cell such that an amount of current for discriminating between gray scale levels is approximately tens of micro-amps.

1. A driving circuit for an electro-luminescence (EL) cell, comprising:
 an EL cell; 
 a supply circuit selectively applying current to the EL cell based on a pixel signal from a data line, the supply circuit including a first transistor connected between the EL cell and a voltage supply line and a charge storage device storing a charge based on the pixel signal; and 
 a control circuit controlling current flow from the supply circuit to the EL cell, the control circuit including a second transistor connected between the data line and the voltage supply line such that the first and second transistors form a current mirror, the first and second transistors having gates connected to the charge storage device.device; 
 a third transistor connected between a data supply line and the second transistor, and a gate of the third transistor connected to a gate signal supply line; 
 a first node connected between the third transistor and the second transistor; and 
 a fourth transistor connected between the first node and the gate of the first transistor and between the first node and the gate of the second transistor, and a gate of the fourth transistor connected to the gate signal supply line. 
 
     
     
       2. The driving circuit of  claim 1 , wherein the second transistor has a channel widthof-to-length ratio that is 3 to 20 times greater than a channel width-to-length ratio of the first transistor. 
     
     
       3. The driving circuit of claim  2  1, wherein the first transistor has a channel widthof-to-length ratio that is 3 to 10 times greater than a channel width-to-length ratio of the second transistor. 
     
     
       4. The driving circuit of  claim 1 , further comprising:
 a third transistor connected between a data supply line and the second transistor, and a gate of the third transistor connected to a gate signal supply line; and   a fourth transistor connected between the third transistor and the gates of the first and second transistors, and a gate of the fourth transistor connected to the gate signal supply line.   
     
     
       5. The driving circuit of  claim 1 , further comprising:
 an enable circuit selectively connecting the supply and control circuits to the data line based on a gate signal. 
 
     
     
       6. An electrode luminescence panel comprising the driving circuit for the electro-luminescence cell as described in  claim 1 . 
     
     
       7. The driving circuit of  claim 1 , wherein an amount of current for discriminating between gray scale levels is approximately tens of micro-amps. 
     
     
       8. A driving circuit for an electro-luminescence (EL) cell, comprising:
 an EL cell; 
 a supply circuit selectively applying current to the EL cell based on a pixel signal from a data line, the supply circuit including a first transistor connected between the EL cell and a voltage supply line and receiving a voltage dependent on the pixel signal at a gate thereof; 
 a control circuit controlling current flow from the supplying circuit to the EL cell, the control circuit including a second transistor connected between the data line and the voltage supply line and a gate of the second transistor being connected to the gate of the first transistor; and 
 a third transistor connected between a data supply line and the second transistor, and a gate of the third transistor connected to a gate signal supply line; 
 a first node connected between the third transistor and the second transistor; 
 a fourth transistor connected between the first node and the gate of the first transistor and between the first node and the gate of the second transistor, and a gate of the fourth transistor connected to the gate signal supply line; and  
 a charge storage device connected between the gates of the first and second transistors and the voltage supply line. 
 
     
     
       9. The driving circuit of  claim 8 , wherein the second transistor has a channel widthof-to-length ratio that is 3 to 20 times greater than a channel width-to-length ratio of the first transistor. 
     
     
       10. The driving circuit of claim  9  8, wherein the first transistor has a channel widthof-to-length ratio that is 3 to 10 times greater than a channel width-to-length ratio of the second transistor. 
     
     
       11. The driving circuit of  claim 8 , further comprising:
 a third transistor connected between a data supply line and the second transistor, a gate of the third transistor connected to a gate signal supply line; and   a fourth transistor connected between the third transistor and the gates of the first and second transistors, a gate of the fourth transistor connected to a gate signal supply line.   
     
     
       12. A driving circuit for an electro-luminescence (EL) cell, comprising:
 an EL cell; 
 a current mirror including a first and a second transistor, the first transistor supplying current to the EL cell based on a pixel signal, and the second transistor controlling the supply of current through the first transistor, the first and second transistors having gates connected to a charge storage device.device; 
 a third transistor connected between a data supply line and the second transistor, and a gate of the third transistor connected to a gate signal supply line; 
 a first node connected between the third transistor and the second transistor; and 
 a fourth transistor connected between the first node and the gate of the first transistor and between the first node and the gate of the second transistor, and a gate of the fourth transistor connected to the gate signal supply line. 
 
     
     
       13. The driving circuit of  claim 12 , wherein the a channel width-to-length ratio of the first transistor is 3 to 10 times greater than the a channel width-to-length ratio of the second transistor. 
     
     
       14. The driving circuit of  claim 12 , further comprising:
 an enabling circuit selectively enabling operation of the current mirror based on a gate signal. 
 
     
     
       15. A The driving circuit of  claim 12 , wherein the second transistor has a channel width-to-length ratio that is 2 to 20 times greater than a channel width-to-length ratio of the first transistor. 
     
     
       16. A driving circuit for an electro-luminescence (EL) cell, comprising:
 an EL cell; and 
 a current mirror including a first transistor and a second transistor, the first transistor supplying current to the EL cell based on a pixel signal, and the second transistor controlling the supply of current through the first transistor, a channel width-to-length ratio of the second transistor formed to be a ratio of a channel width-to-length ratio of the first transistor.transistor; 
 a third transistor connected between a data supply line and the second transistor, and a gate of the third transistor connected to a gate signal supply line; 
 a first node connected between the third transistor and the second transistor; and 
 a fourth transistor connected between the first node and the gate of the first transistor and between the first node and the gate of the second transistor, and a gate of the fourth transistor connected to the gate signal supply line. 
 
     
     
       17. The driving circuit of claim 1, wherein the second transistor has a current capacity greater than a current capacity of the first transistor. 
     
     
       18. The driving circuit of claim 1, wherein the first transistor has a current capacity greater than a current capacity of the second transistor. 
     
     
       19. The driving circuit of claim 1, wherein the second transistor has a channel dimension greater than a channel dimension of the first transistor. 
     
     
       20. The driving circuit of claim 1, wherein the first transistor has a channel dimension greater than a channel dimension of the second transistor. 
     
     
       21. The driving circuit of claim 1, wherein the second transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the first transistor. 
     
     
       22. The driving circuit of claim 1, wherein the first transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the second transistor. 
     
     
       23. The driving circuit of claim 8, wherein the second transistor has a current capacity greater than a current capacity of the first transistor. 
     
     
       24. The driving circuit of claim 8, wherein the first transistor has a current capacity greater than a current capacity of the second transistor. 
     
     
       25. The driving circuit of claim 8, wherein the second transistor has a channel dimension greater than a channel dimension of the first transistor. 
     
     
       26. The driving circuit of claim 8, wherein the first transistor has a channel dimension greater than a channel dimension of the second transistor. 
     
     
       27. The driving circuit of claim 8, wherein the second transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the first transistor. 
     
     
       28. The driving circuit of claim 8, wherein the first transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the second transistor. 
     
     
       29. The driving circuit of claim 12, wherein the second transistor has a current capacity greater than a current capacity of the first transistor. 
     
     
       30. The driving circuit of claim 12, wherein the first transistor has a current capacity greater than a current capacity of the second transistor. 
     
     
       31. The driving circuit of claim 12, wherein the second transistor has a channel dimension greater than a channel dimension of the first transistor. 
     
     
       32. The driving circuit of claim 12, wherein the first transistor has a channel dimension greater than a channel dimension of the second transistor. 
     
     
       33. The driving circuit of claim 12, wherein the second transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the first transistor. 
     
     
       34. The driving circuit of claim 12, wherein the first transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the second transistor. 
     
     
       35. The driving circuit of claim 16, wherein the second transistor has a current capacity greater than a current capacity of the first transistor. 
     
     
       36. The driving circuit of claim 16, wherein the first transistor has a current capacity greater than a current capacity of the second transistor. 
     
     
       37. The driving circuit of claim 16, wherein the second transistor has a channel dimension greater than a channel dimension of the first transistor. 
     
     
       38. The driving circuit of claim 16, wherein the first transistor has a channel dimension greater than a channel dimension of the second transistor. 
     
     
       39. The driving circuit of claim 16, wherein the second transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the first transistor. 
     
     
       40. The driving circuit of claim 16, wherein the first transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the second transistor.