Control circuitry for a non-volatile memory

Abstract

Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row Row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.

1. Circuitry that applies voltages to a memory to perform applications wherein said memory includes plurality of memory cells, said plurality of memory cells organized in rows and columns, said circuitry A circuit, comprising:
 Firstfirst circuitry that appliesconfigured to apply one of a first plurality of voltages to at least one of said a plurality of memory cells based upon a row in which said at least one of said plurality of memory cells is arranged and based upon an application to be performed by said at least one of said plurality of memory cells, said first circuitry including row latch circuitry having a first input that receives configured to receive one of a plurality of high voltages and a second input receives configured to receive one of a plurality of low voltages and an a first output for selectively applying one of configured to selectively apply said one of said plurality of high voltages and or said one of said plurality of low voltages to said at least one of said plurality of memory cells; and 
 Secondsecond circuitry that appliesconfigured to apply one of a secondsaid plurality of voltages to said at least one of said plurality of memory cells based upon a column in which said at least one of said plurality of memory cells is organizedarranged and based upon said application to be performed by said at least one of said plurality of memory cells; 
 wherein said second circuitry includes column latch circuitry having a third input configured to receive a first group of said plurality of high voltages, a fourth input configured to receive a second group of said plurality of high voltages, a fifth input configured to receive one of said plurality of low voltages, and a second output configured to selectively apply said one of said plurality of high voltages or said one of said plurality of low voltages to said at least one of said plurality of memory cells. 
 
     
     
       2. The circuitry circuit of  claim 1  where in said first circuitry further comprises:
 Aa high voltage multiplexormultiplexer having a plurality of multiplexer inputs that each receives multiplexer input configured to receive one of said plurality of high voltages and an a multiplexer output for applying said one of said plurality of high voltages to said row latch circuitry. 
 
     
     
       3. The circuitry circuit of  claim 2  wherein one of said plurality of high voltages is a VCC voltage. 
     
     
       4. The circuitry circuit of  claim 3  wherein said VCC voltage is 2.5 volts. 
     
     
       5. The circuitry circuit of  claim 2  wherein one of said plurality of high voltages is VPP. 
     
     
       6. The circuitry circuit of  claim 5  where wherein said VPP voltage is 15 volts. 
     
     
       7. The circuitry circuit of  claim 2  wherein one of said plurality of high voltages is VPP 1 . 
     
     
       8. The circuitry circuit of  claim 7  wherein said VPP 1  voltage is 10 volts. 
     
     
       9. The circuitry circuit of  claim 1  further comprising:
 a low voltage multiplexer having a plurality of multiplexer inputs wherein, each of said plurality of inputs receives multiplexer inputs configured to receive one of said plurality of low voltages, and an a multiplexer output that selectively applies configured to selectively apply said one of said plurality of low voltages to said row latch circuitry. 
 
     
     
       10. The circuitry circuit of  claim 9  wherein one of said plurality of low voltages is VSS. 
     
     
       11. The circuitry circuit of  claim 10  wherein said VSS voltage is 0 volts. 
     
     
       12. The circuitry circuit of  claim 9  wherein one of said plurality of low voltages is VPP 2 . 
     
     
       13. The circuitry circuit of  claim 12  wherein said VPP 2  voltage is 5 volts. 
     
     
       14. The circuitry circuit of  claim 1  further comprising:
 Selectionselection circuitry that appliesconfigured to apply a signal to said row latch circuitry to determine said one of said one of said plurality of high voltages and said one of said plurality of low voltages applied to said at least one of said plurality of memory cells. 
 
     
     
       15. The circuitry circuit of  14  wherein said selection circuitry comprises:
 a signal line; 
 an inverter connected to said signal line; and 
 a world line multiplexor multiplexer having a first word line input connected to said signal line and, a second word line input connected to said inverter an inverter output, and an a word line output that selectively applies configured to selectively apply one of said signal and line or an inverted signal to said row latch circuitry; and 
 wherein said row latch circuit selectively applies circuitry is configured to selectively apply said one of said one of said plurality of high voltages and said one of said plurality of low voltages to said at least one of said plurality of memory cells. 
 
     
     
       16. The circuitry of  claim 1  wherein said second circuitry comprises:
 column latch circuitry having a first input that receives a one of a plurality of high voltages and a second input that receives a one of a plurality of low voltages and an output that applies a one of said one of said plurality of high voltages and said one of said plurality of low voltages to said at least one of said plurality of memory cells. 
 
     
     
       17. The circuitry circuit of claim  16  1 wherein said second circuitry further comprises:
 word latch circuitry having a plurality of inputs for receiving said plurality of high voltages and an a first word latch input configured to receive one of said first group of said plurality of high voltages, a second word latch input configured to receive one of said second group of said plurality of high voltages, and a word latch output for selectively applying said one of said plurality of high voltages to said column latch circuitry configured to selectively apply the one of the first group of said plurality of high voltages or the one of the second group of said plurality of high voltages to a column latch circuit. 
 
     
     
       18. The circuitry circuit of  claim 17  wherein said second circuitry further comprises:
 a first multiplexer having a plurality of first multiplexer inputs wherein each of said plurality of inputs receives a one of a first plurality of high voltages to said word latch, and having an output that applies one of said first plurality of high voltages to an configured to receive the first group of said plurality of high voltages and having a first multiplexer output configured to apply one of the first group of said plurality of high voltages to the first word latch input of said word latch circuitry. 
 
     
     
       19. The circuitry circuit of  claim 18  wherein said second circuitry further comprises:
 a second multiplexer having a plurality of second multiplexer inputs wherein each of said plurality of inputs receives a one of a second plurality of high voltages to said word latch, and having an output that applies one of said second plurality of high voltages to an configured to receive the second group of said plurality of high voltages and having a second multiplexer output configured to apply one of the second group of said plurality of high voltages to the second word latch input of said word latch circuitry. 
 
     
     
       20. The circuitry circuit of  claim 17  wherein said word latch circuitry further comprises:
 a set signal input that receives configured to receive a set signal; 
 a reset signal input that receives an input configured to receive a reset signal; and 
 circuitry that applies said one of said one of said plurality of high voltages and said one of said plurality of low voltages to said column latch circuitry configured to selectively apply the one of the first group of said plurality of high voltages or the one of the second group of said plurality of high voltages to a column latch circuit in response to the set signal or the reset signal. 
 
     
     
       21. The circuitry circuit of  claim 17  wherein one of said plurality of high voltages is VCC. 
     
     
       22. The circuitry circuit of  claim 21  wherein said VCC voltage is 2.5 volts. 
     
     
       23. The circuitry circuit of  claim 17  wherein one of said plurality of high voltages is VPP. 
     
     
       24. The circuitry circuit of  claim 23  wherein said VPP voltage is 15 volts. 
     
     
       25. The circuitry circuit of  claim 17  wherein one of said plurality of high voltages is VPP 1 . 
     
     
       26. The circuitry circuit of  claim 25  wherein said VPP 1  voltage is 10 volts. 
     
     
       27. The circuitry circuit of claim  16  further comprising 1 wherein said second circuitry further comprises:
 a low voltage multiplexer having a plurality of input wherein multiplexer inputs, each of said plurality of input receives multiplexer inputs configured to receive one of said plurality of low voltage signals voltages, and having an a multiplexer output that selectively applies configured to selectively apply said one of said plurality of low voltage signals voltages to said column latch circuitry. 
 
     
     
       28. The circuitry circuit of  claim 27  wherein one of said plurality of low voltages is VSS. 
     
     
       29. The circuitry circuit of  claim 28  wherein said VSS voltage is 0 volts. 
     
     
       30. The circuitry circuit of  claim 27  wherein one of said plurality of low voltages is said low voltages VPP 2 . 
     
     
       31. The circuitry circuit of  claim 30  wherein said VPP 2  voltage is 5 volts. 
     
     
       32. A method for applying voltages to a memory to perform applications wherein said memory includes plurality of memory cells, said plurality of memory cells organized in rows and columns, said method, comprising:
 applying one a first of a first plurality of voltages to at least one of said a plurality of memory cells based upon a row in which said at least one of said the plurality memory cells is arranged and based upon an application to be performed by said at least one of said the plurality of memory cells, wherein said step of applying one of said first the first of the plurality of voltages comprises: 
 receiving one of a plurality of high voltages,; 
 receiving one of a plurality of low voltages,; and 
 selecting one of said one of said plurality of high voltage and said one of said plurality of low voltages, and applying said selected one of said voltages to said at least one of said plurality of memory cells; and 
 applying said one of the plurality of high voltages or said one of the plurality of low voltages to at least one word line corresponding to said at least one of the plurality of memory cells; and 
 applying a one of a second of the plurality of voltages to said at least one of a the plurality of memory cells based upon a column in which said at least one of said the plurality of memory cells is organized arranged and based upon said application to be performed by said at least one of said the plurality of memory cells, wherein said applying the second of the plurality of voltages comprises: 
 receiving a first group of the plurality of high voltages at a first input of a column latch circuit; 
 receiving a second group of the plurality of high voltages at a second input of said column latch circuit; 
 receiving said one of the plurality of low voltages at a third input of said column latch circuit; and 
 selectively applying said first group of the plurality of high voltages, said second group of the plurality of high voltages, or said one of the plurality of low voltages to at least one bitline corresponding to said at least one of the plurality of memory cells. 
 
     
     
       33. The method of  claim 32  wherein said step of applying one of said first plurality of voltages further comprises:
 receiving said plurality of high voltages; and 
 selecting said one of said plurality of high voltages. 
 
     
     
       34. The method of claim  33  32 wherein one of said the plurality of high voltages is includes a VCC voltage. 
     
     
       35. The method of  claim 34  wherein said VCC voltage is 2.5 volts. 
     
     
       36. The method of claim  33  32 wherein one of said the plurality of high voltages is VPP includes a VPP voltage. 
     
     
       37. The method of  claim 36  where wherein said VPP voltage is 15 volts. 
     
     
       38. The method of claim  33  32 wherein one of said the plurality of high voltages is includes a VPP 1  voltage. 
     
     
       39. The method of  claim 38  wherein said VPP 1  voltage is 10 volts. 
     
     
       40. The method of  claim 32  further comprising:
 receiving said plurality of low voltages; and 
 selecting said one of said plurality of low voltages. 
 
     
     
       41. The method of claim  40  32 wherein one of said the plurality of low voltages is includes a VSS voltage. 
     
     
       42. The method of  claim 41  wherein said VSS voltage is 0 volts. 
     
     
       43. The method of claim  40  32 wherein one said the plurality of low voltages is includes a VPP 2  voltage. 
     
     
       44. The method of  claim 43  wherein said VPP 2  voltage is 5 volts. 
     
     
       45. The method of  claim 32  further comprising:
 receiving a selection signal; 
 determining said one of said one of said plurality of high voltages and said one of said plurality of low voltages to apply to said at least one of said plurality of memory cells responsive to receiving said selection signal 
 applying said one of the plurality of high voltages or said one of the plurality of low voltages to said at least one of the plurality of memory cells in response to a selection signal. 
 
     
     
       46. The method of  claim 32  wherein said applying said one of said second plurality of voltages comprises:
 receiving one of a plurality of high voltages; 
 receiving one of a plurality of low voltages; 
 selecting one of said one of said plurality of high voltages and said one of said plurality of low voltages; and 
 applying said selected one of said voltages to said at least one of said plurality of memory cells. 
 
     
     
       47. The method of  claim 46  wherein said applying said one of said second plurality of voltages further comprises:
 receiving said plurality of high voltages; and 
 determining said one of said plurality of high voltages. 
 
     
     
       48. The method of claim  47  32 further comprising:
 receiving a set signal; 
 receiving a reset signal; and 
 determining said one of said one of said plurality of high voltages and said one of said plurality of low voltages responsive to receiving said set signal and said reset signal 
 applying said first group of the plurality of high voltages, said second group of the plurality of high voltages, or said one of the plurality of low voltages to said at least one bitline in response to the set and reset signals. 
 
     
     
       49. The method of claim  47  32 wherein one of said first group of the plurality of high voltages is includes a VCC voltage. 
     
     
       50. The method of  claim 49  wherein said VCC voltage is 2.5 volts. 
     
     
       51. The method of claim  47  32 wherein one of said second group of the plurality of high voltages is includes a VPP voltage. 
     
     
       52. The method of  claim 51  wherein said VPP voltage is 15 volts. 
     
     
       53. The method of claim  47  32 wherein one of said first group of the plurality of high voltages is includes a VPP 1  voltage. 
     
     
       54. The method of  claim 53  wherein said VPP 1  voltage is 10 volts. 
     
     
       55. The method of  claim 46  further comprising:
 receiving said plurality of low voltage signals; and 
 determining said one of plurality of low voltage signals. 
 
     
     
       56. The method of claim  55  32 wherein one of said the plurality of low voltages is includes a VSS voltage. 
     
     
       57. The method of  claim 56  wherein said VSS voltage is 0 volts. 
     
     
       58. The method of claim  55  32 wherein one of said the plurality of low voltages is said low voltages is includes a VPP 2  voltage. 
     
     
       59. The method of  claim 58  wherein said VPP 2  voltage is 5 volts. 
     
     
       60. A memory comprising:
 a plurality of memory cells arranged in an array of rows and columns; and   circuitry configured to apply voltages to said memory to perform applications, wherein said circuitry includes:
 first circuitry configured to apply one of a first plurality of voltages to at least one of said plurality of memory cells based, at least in part, upon a row in which said at least one of said plurality of memory cells is arranged and an application to be performed by said at least one of said plurality of memory cells; and 
 second circuitry configured to apply one of a second plurality of voltages to said at least one of said plurality of memory cells based, at least in part, upon a column in which said at least one of said plurality of memory cells is arranged and said application to be performed by said at least one of said plurality of memory cells; 
 wherein the first plurality of voltages comprises a first plurality of high voltages and a second plurality of high voltages; 
 wherein said first circuitry further comprises row latch circuitry having a first input configured to receive one of the first plurality of high voltages and a second input configured to receive one of the second plurality of high voltages; 
 wherein said first circuitry further comprises a third input configured to receive one of a plurality of low voltages; and 
 wherein said first circuitry further comprises a first output configured to selectively apply said one of said first plurality of high voltages, said one of said second plurality of high voltages, or said one of said plurality of low voltages to said at least one of said plurality of memory cells. 
   
     
     
       61. The memory of claim 60, wherein said first circuitry further comprises:
 a high voltage multiplexer configured to apply at least one high voltage from the first plurality of voltages to a row latch circuitry.   
     
     
       62. The memory of claim 61, wherein said at least one of the first plurality of high voltage or said at least one of the second plurality of high voltages comprises a VCC voltage. 
     
     
       63. The memory of claim 62, wherein said VCC voltage comprises 2.5 volts. 
     
     
       64. The memory of claim 61, wherein said at least one of the first plurality of high voltage or said at least one of the second plurality of high voltages comprises a VPP voltage. 
     
     
       65. The memory of claim 64, wherein said VPP voltage comprises 15 volts. 
     
     
       66. The memory of claim 61, wherein said at least one of the first plurality of high voltage or said at least one of the second plurality of high voltages comprises a VPP1 voltage. 
     
     
       67. The memory of claim 66, wherein said VPP1 voltage comprises 10 volts. 
     
     
       68. The memory of claim 61, further comprising:
 a low voltage multiplexer configured to apply said one of the plurality of low voltages to the row latch circuitry.   
     
     
       69. The memory of claim 68, wherein said one of the plurality of low voltages comprises a VSS voltage. 
     
     
       70. The memory of claim 69, wherein said VSS voltage comprises 0 volts. 
     
     
       71. The memory of claim 68, wherein said one of the plurality of low voltages comprises a VPP2 voltage. 
     
     
       72. The memory of claim 71, wherein said VPP2 voltage comprises 5 volts. 
     
     
       73. The memory of claim 60 wherein said first circuitry further comprises:
 an input terminal configured to receive a signal;   an inverter configured to generate an inverted signal in response to the signal; and   a word line multiplexer configured to select the signal or the inverted signal in response to a mode signal.   
     
     
       74. A method, comprising:
 applying one of a first plurality of voltages to a memory cell based, at least in part, on a row in which said memory cell is arranged and an application to be performed by said memory cell; and   applying one of a second plurality of voltages to said memory cell based, at least in part, on a column in which said memory cell is arranged and said application to be performed by said memory cell;   wherein said applying said one of said second plurality of voltages comprises:
 receiving a first of a plurality of high voltages; 
 receiving a second of said plurality of high voltages; 
 receiving one of a plurality of low voltages; and 
 applying the first of said plurality of high voltages, the second of said plurality of high voltages, or said one of said plurality of low voltages to said memory cell. 
   
     
     
       75. The method of claim 74, wherein said plurality of high voltages includes a VCC voltage. 
     
     
       76. The method of claim 75, wherein said VCC voltage is 2.5 volts. 
     
     
       77. The method of claim 74, wherein said plurality of high voltages includes a VPP voltage. 
     
     
       78. The method of claim 77, wherein said VPP voltage is 15 volts. 
     
     
       79. The method of claim 74, wherein said plurality of high voltages includes a VPP1 voltage. 
     
     
       80. The method of claim 79, wherein said VPP1 voltage is 10 volts. 
     
     
       81. The method of claim 74, wherein said plurality of low voltages includes a VSS voltage. 
     
     
       82. The method of claim 81, wherein said VSS voltage is 0 volts. 
     
     
       83. The method of claim 74, wherein said plurality of low voltages includes a VPP2 voltage. 
     
     
       84. The method of claim 83, wherein said VPP2 voltage is 5 volts. 
     
     
       85. The method of claim 74, further comprising:
 applying one of said first plurality of voltages to said memory cell in response to receiving a selection signal.