Method and apparatus for simulating logic circuits that include a circuit block to which power is not supplied

Abstract

A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.

1. A logic circuit simulation apparatus for simulating a logic circuit which includes a plurality of circuit blocks, the apparatus comprising:
 a power control signal specifying unit configured to create power control signal information for specifying statuses of a plurality of power control signals in the logic circuit; 
 a logic circuit simulation control information generation unit configured to read the power control signal information created by the power control signal specifying unit and to read circuit connection information, said logic circuit simulation control information generation unit configured to generate logic circuit simulation control information based on the power control signal information and the circuit connection information; and 
 a logic circuit simulation unit configured to fix with high impedance each input of a circuit block among the plurality of circuit blocks when said circuit block is not supplied with power in accordance with the logic circuit simulation control information and release the high impedance from each from each input of said circuit block when said circuit block is to be supplied with power in accordance with release control information of the logic circuit simulation control information, said logic circuit simulation unit configured to simulate the logic circuit. 
 
     
     
       2. The logic circuit simulation apparatus according to  claim 1 , further comprising:
 a delay time specifying unit to specify a power-off delay time for the circuit block to which power is not to be supplied. 
 
     
     
       3. The logic circuit simulation apparatus according to  claim 2 , wherein the delay time specifying unit is further configured to specify a power-on delay time of release control information generated by the logic circuit simulation apparatus. 
     
     
       4. A method for simulating a logic circuit which includes a plurality of circuit blocks comprising the steps of:
 creating power control signal information for specifying statuses of a plurality of power control signals; 
 reading the power control signal information and circuit connection information; 
 generating logic circuit simulation control information based on the power control signal information and the circuit connection information; 
 reading the logic circuit simulation control information for instructing a logic circuit simulation unit to fix with high impedance each input of a circuit block to which power is not supplied and to release the high impedance of each input of from the circuit block when power is to be supplied; and 
 simulating the logic circuit in accordance with the logic circuit simulation control information. 
 
     
     
       5. The method for simulating a logic circuit which includes a plurality of circuit blocks according to  claim 4 , comprising further steps of:
 specifying delay time from a time the power control signal is changed to a time the power to the circuit block is changed as a result of the change in the power control signal; 
 reading the delay time; and 
 generating logic circuit simulation control information based on the power control signal information, the delay time and the circuit connection information. 
 
     
     
       6. The method for simulating a logic circuit which includes a plurality of circuit blocks according to  claims 4  or  5 , comprising further steps of:
 adding buffer circuits at the inputs of the circuit blocks. 
 
     
     
       7. A logic circuit simulation apparatus for simulating a logic circuit which includes a plurality of circuit blocks, the apparatus comprising:
 power control signal specifying means for creating power control signal information for specifying statuses of a plurality of power control signals; 
 logic circuit simulation control information generation means for reading the power control signal information created by the power control signal specifying means and for reading circuit connection information, said logic circuit simulation control information generation means configured to generate logic circuit simulation control information based on the power control signal information and the circuit connection information; and 
 logic circuit simulation means for fixing with high impedance each input of a circuit block of the plurality of circuit blocks, when said circuit block is not supplied with power in accordance with the logic circuit simulation control information and for releasing the high impedance from each input of said circuit block when said circuit block is to be supplied with power in accordance with the logic circuit simulation control information, said logic circuit simulation means configured to simulate the logic circuit. 
 
     
     
       8. A logic circuit simulation apparatus for simulating a logic circuit which includes a plurality of circuit blocks, the apparatus comprising:
 a power control signal specifying unit configured to create power control signal information for specifying statuses of a plurality of power control signals in the logic circuit;   a logic circuit simulation control information generation unit configured to read the power control signal information created by the power control signal specifying unit and to read circuit connection information, said logic circuit simulation control information generation unit configured to generate logic circuit simulation control information based on the power control signal information and the circuit connection information; and   a logic circuit simulation unit configured to fix with high impedance a circuit block among the plurality of circuit blocks when said circuit block is not supplied with power in accordance with the logic circuit simulation control information and release the high impedance from said circuit block when said circuit block is to be supplied with power in accordance with release control information of the logic circuit simulation control information, said logic circuit simulation unit configured to simulate the logic circuit.   
     
     
       9. A logic circuit as in claim 8 in which said logic circuit simulation unit is configured to fix with high impedance an input of said circuit block when the circuit block is not supplied with power in accordance with the logic circuit simulation control information and release the high impedance from the input of said circuit block when said circuit block is to be supplied with power in accordance with release control information of the logic circuit simulation control information, said logic circuit simulation unit configured to simulate the logic circuit. 
     
     
       10. A logic circuit as in claim 8 in which said logic circuit simulation unit is configured to fix with high impedance an input and an output of said circuit block when the circuit block is not supplied with power in accordance with the logic circuit simulation control information and release the high impedance from the input and the output of said circuit block when said circuit block is to be supplied with power in accordance with release control information of the logic circuit simulation control information, said logic circuit simulation unit configured to simulate the logic circuit. 
     
     
       11. A logic circuit as in claim 8 in which said logic circuit simulation unit is configured to fix with high impedance an output of said circuit block when the circuit block is not supplied with power in accordance with the logic circuit simulation control information and release the high impedance from the output of said circuit block when said circuit block is to be supplied with power in accordance with release control information of the logic circuit simulation control information, said logic circuit simulation unit configured to simulate the logic circuit. 
     
     
       12. A logic circuit simulation apparatus configured to simulate a logic circuit by reading and using previously provided circuit connection information, comprising:
 a power control signal specifying means configured to generate power control signal information specifying a power control signal name for controlling a stop and a start of a power supply to each circuit block constituting the logic circuit and a circuit block name for a target control block; and   a logic circuit simulation control information generating means configured to:
 read the circuit connection information and the power control signal information generated by the power control signal specifying means for stopping the power supply to the target control block; 
 read the target control block corresponding to the read circuit block name specified by the read power control signal information from the circuit connection information; and 
 generate logic circuit simulation control information to instruct the logic circuit simulation means to make the target control block to have a logical value X while the power supply to the target control block is stopped, wherein logical value X is an unfixed value that is not a logical “1” or a logical “0,” 
 wherein the logic circuit simulation means simulates, by reading and using the logic circuit simulation control information generated by the logic circuit simulation control information generating means, and the circuit connection information, a state when the power supply to the target control block is stopped; and 
   the logic circuit simulation control information generating means also configured to:
 read the circuit connection information and the power control signal information generated by the power control signal specifying means for starting the power supply to the target control block; and 
 generate logic circuit simulation control information to instruct the logic circuit simulation means to release the logical value X state of the target control block when the power supply is started, 
 wherein the logic circuit simulation means is configured to simulate the state in which the power supply to the target control block has started by reading and using the logic circuit simulation control information generated by the logic circuit simulation control information generating means. 
   
     
     
       13. A logic circuit simulation apparatus as claimed in claim 12, further comprising:
 a power delay time specifying means configured to generate power delay time information to specify a stop delay time from a time when a state of a power control signal is changed until a time when the power supply to the target control block is actually stopped, wherein   the logic circuit simulation control information generating means generates, by reading and using the power delay time information generated by the power delay time specifying means, the power control signal information generated by the power control signal specifying means for causing the power supply to the target control block to stop, and the circuit connection information, the logic circuit simulation control information including information to instruct the logic circuit simulation means to make the control target circuit to have the logical value X state after the stop delay time specified in the power delay time information; and wherein   the logic circuit simulation means is configured to simulate, by reading and using the logic circuit simulation control information generated by the logic circuit simulation control information generating means, the state when the power supply to the target control block is stopped including the stop delay time.   
     
     
       14. A logic circuit simulation apparatus as claimed in claim 13, wherein:
 the power delay time specifying means generates the power delay time information including information specifying the start delay time from when the power control signal is changed until when the power supply to the target control block actually starts;   the logic circuit simulation control information generation means generates, by reading and using the power delay time information generated by the power delay time specifying means, the power control signal information generated by the power control signal specifying means for causing the power supply to the target control block to start, and the circuit connection information, the logic circuit simulation control information including information to instruct the logic circuit simulation means to release the target control block from a state of logical value X after the start delay time specified by the power delay time information; and   the logic circuit simulation means simulates, by reading and using the logic circuit simulation control information generated by the logic circuit simulation control information generation means, the target control block including the start delay time.   
     
     
       15. A method for using a logic circuit simulator to simulate a logic circuit by reading and using previously provided circuit connection information, comprising:
 using a power control signal specifying unit in the logic circuit simulator to generate power control signal information specifying a power control signal name for controlling a stop and a start of a power supply to each circuit block constituting the logic circuit and a circuit block name for a target control block;   using a logic circuit simulation control information generation unit in the logic circuit simulator to read the circuit connection information and the power control signal information for stopping the power supply to the target control block;   using the logic circuit simulation control information generation unit to read the target control block corresponding to the read circuit block name specified by the read power control signal information from the circuit connection information;   using the logic circuit simulation control information generation unit to generate logic circuit simulation control information to make the target control block have a logical value X while the power supply to the target control block is stopped, wherein logical value X is an unfixed value that is not a logical “1” or a logical “0”;   using a logic circuit simulation unit in the logic circuit simulator to simulate, by reading and using the logic circuit simulation control information and the circuit connection information, a state when the power supply to the target control block is stopped;   generating, by reading the circuit connection information and the power control signal information for starting the power supply to the target control block, the logic circuit simulation control information including instructions to release the logical value X state of the target control block when the power supply is started; and   simulating the state in which the power supply to the target control block has started by reading and using the logic circuit simulation control information.   
     
     
       16. The method as claimed in claim 15, further comprising:
 generating power delay time information to specify a stop delay time from a time when a state of a power control signal is changed until a time when the power supply to the target control block is actually stopped;   generating, by reading and using the power delay time information, the power control signal information for causing the power supply to the target control block to stop and the circuit connection information, the logic circuit simulation control information including instructions to make the control target circuit have the logical value X state after the stop delay time specified in the power delay time information; and   simulating, by reading and using the logic circuit simulation control information, the state when the power supply to the target control block is stopped including the stop delay time.   
     
     
       17. The method as claimed in claim 16, further comprising:
 generating the power delay time information including information specifying the start delay time from when the power control signal is changed until when the power supply to the target control block actually starts;   generating, by reading and using the power delay time information, the power control signal information for causing the power supply to the target control block to start and the circuit connection information, the logic circuit simulation control information including instructions to release the target control block from a state of logical value X after the start delay time specified by the power delay time information; and   simulating, by reading and using the logic circuit simulation control information, the target control block including the start delay time.   
     
     
       18. A method for simulating a logic circuit which includes a plurality of circuit blocks comprising the steps of:
 creating power control signal information for specifying statuses of a plurality of power control signals;   reading the power control signal information and circuit connection information;   generating logic circuit simulation control information based on the power control signal information and the circuit connection information;   reading the logic circuit simulation control information for instructing a logic circuit simulation unit to fix a circuit block to which power is not supplied with an impedance sufficient to prevent an input to the circuit block of value “1” or “0” from resulting in an output value of either “1” or “0” and to release the impedance from the circuit block when power is to be supplied; and   simulating the logic circuit in accordance with the logic circuit simulation control information.   
     
     
       19. The method for simulating a logic circuit which includes a plurality of circuit blocks according to claim 18, comprising further steps of:
 specifying delay time from a time the power control signal is changed to a time the power to the circuit block is changed as a result of the change in the power control signal;   reading the delay time; and   generating logic circuit simulation control information based on the power control signal information, the delay time and the circuit connection information.   
     
     
       20. A logic circuit simulation apparatus configured to simulate a logic circuit by reading and using previously provided circuit connection information, comprising:
 a power control signal specifying means configured to generate power control signal information specifying a power control signal name for controlling a stop and a start of a power supply to each circuit block constituting the logic circuit and a circuit block name for a target control block; and   a logic circuit simulation control information generating means configured to:
 read the circuit connection information and the power control signal information generated by the power control signal specifying means for stopping the power supply to the target control block; 
 read the target control block corresponding to the read circuit block name specified by the read power control signal information from the circuit connection information; and 
 generate logic circuit simulation control information to instruct the logic circuit simulation means to make the target control block to have a logical value X while the power supply to the target control block is stopped, wherein logical value X is a value that is not a logical “1” or a logical “0,” 
 wherein the logic circuit simulation means simulates, by reading and using the logic circuit simulation control information generated by the logic circuit simulation control information generating means, and the circuit connection information, a state when the power supply to the target control block is stopped; and 
   the logic circuit simulation control information generating means also configured to:
 read the circuit connection information and the power control signal information generated by the power control signal specifying means for starting the power supply to the target control block; and 
 generate logic circuit simulation control information to instruct the logic circuit simulation means to release the logical value X state of the target control block when the power supply is started, 
 wherein the logic circuit simulation means is configured to simulate the state in which the power supply to the target control block has started by reading and using the logic circuit simulation control information generated by the logic circuit simulation control information generating means. 
   
     
     
       21. A method for manufacturing a logic integrated circuit, comprising:
 designing the logic circuit by creating circuit connection information for the logic circuit; and   simulating the logic circuit using the circuit connection information, and   wherein simulating the logic circuit further comprises:
 creating power control signal information for specifying statuses of a plurality of power control signals; 
 reading the power control signal information and circuit connection information; 
 generating logic circuit simulation control information based on the power control signal information and the circuit connection information; 
 reading the logic circuit simulation control information for instructing a logic circuit simulation unit to fix a circuit block to which power is not supplied with an impedance sufficient to prevent an input to the circuit block of value “1” or “0” from resulting in an output value of either “1” or “0” and to release the impedance from the circuit block when power is to be supplied; and 
 simulating the logic circuit in accordance with the logic circuit simulation control information.