Three-dimensional ladar module with alignment reference insert circuitry

Abstract

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T 0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing. A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

1. An electronic circuit comprised of comprising:
 a photon detector array means for convertingconfigured to convert photons tointo a detector output signal,;  
 a plurality of readout electronics integrated circuit chips, each readout electronics integrated circuit chip comprising including a plurality of channels for receiving configured to receive and processing process output signals generated by said the photon detector array, wherein said the plurality of readout electronics integrated circuit chips are arranged in a stacked configuration, with each of said the readout electronics integrated circuit chips forming one layer of said the stacked configuration, and wherein said the photon detector array is bonded to a lateral surface of said the stacked configuration perpendicular to said the stacked configuration and is connected to the plurality of channels via a plurality of T-connects disposed on said the lateral surface of said the stacked configuration,;  
 wherein at least two of said the plurality of channels comprise, include:
 a converting circuit means for converting said configured to convert the detector output signal to into a digitized data value comprised of comprising one or more digital bits comprising including an image data set, wherein each digital bit has a position in said the image data set,; 
 a reference insert circuit means for inserting configured to insert one or more user-defined reference points at one or more predetermined positions in said the image data set,; and, 
 a reference point synchronization circuit means for synchronizingconfigured to synchronize at least one of saidthe user-defined reference points with at least one other of saidthe user-defined reference points in eachthe image data sets of at least two of said channels' image data setsthe plurality of channels. 
 
 
     
     
       2. The electronic circuit of  claim 1 , further comprising at least one FIFO a first-in, first out (FIFO) shift register for storing said configured to store the image data set. 
     
     
       3. The electronic circuit of  claim 1 , where said wherein the reference point synchronization means circuit is a field programmable field-programmable gate array. 
     
     
       4. The electronic circuit of  claim 1 , wherein said the at least two of the plurality of channels are each defined upon one integrated circuit chip. 
     
     
       5. The electronic circuit of  claim 1 , wherein each of said the at least two of the plurality channels are defined upon separate integrated circuit chips. 
     
     
       6. An electronic circuit comprised of comprising:
 an electronic sensora photon detector array having an output,;  
 a plurality of readout electronics integrated circuit chips, each readout electronics integrated circuit chip comprising including a plurality of channels for receiving and processing configured to receive and process output signals generated by said the photon detector array, wherein said the plurality of readout electronics integrated circuit chips are arranged in a stacked configuration, with each of said the readout electronics integrated circuit chips forming one layer of said the stacked configuration, and wherein said the photon detector array is bonded to a lateral surface of said the stacked configuration perpendicular to said the stacked configuration and is connected to the plurality of channels via a plurality of T-connects disposed on said the lateral surface of said the stacked configuration,;  
 wherein at least two of said the layers comprise include: 
 sensor converting means for converting circuitry configured to convert the output of said the electronic sensor to into a digitized data value,; 
 a storage circuit means for the storing of said configured to store the digitized data value, said the storage circuit means comprising a plurality of individual bin circuit means circuits, each of said the bin circuit means circuits having a variable logic state and each having a storage circuit means position,;  
 a reference insert circuit for selectively asserting configured to selectively assert a predetermined bin logic state in said at least one a preselected bin circuit means, whereby a user-defined reference point may be selectively asserted at the respective storage circuit means positions on each of said the layers,; 
 an output circuit means for the outputting of said configured to output the digitized data value,; and, 
 a reference point synchronization circuit means for the receiving of and synchronizing of saidconfigured to receive and synchronize the outputted digitized data values using saidthe reference points for generatingto generate a plurality of synchronized digitized data values. 
 
 
     
     
       7. The electronic circuit of  claim 6 , wherein said the storage circuit means is comprised of comprises a FIFO first-in, first-out (FIFO) shift register. 
     
     
       8. The electronic circuit of  claim 6 , wherein said synchronizing the reference point synchronization circuit is performed in a field programmable field-programmable gate array. 
     
     
       9. An electronic circuit comprising:
 a photon detector array configured to convert photons into a detector output signal; and   a processing module including a plurality of readout electronics integrated circuit chips (ROICs), wherein each ROIC comprises a plurality of channels configured to receive and process the detector output signal generated by the photon detector array, and wherein the plurality of channels are further configured to convert the detector output signal into an image data set including at least one digital bit;   wherein the plurality of ROICs are arranged in a stacked configuration with each ROIC forming a layer of the stacked configuration; and   wherein the photon detector array is bonded to a lateral surface of the stacked configuration substantially perpendicular to the stacked configuration and is connected to each channel of the plurality of channels via a respective T-connect disposed on the lateral surface of the stacked configuration.   
     
     
       10. The electronic circuit of claim 9, wherein a channel of the plurality of channels comprises a converting circuit configured to convert the detector output signal into an image data set including a digital bit, and wherein the digital bit has a position in the image data set. 
     
     
       11. The electronic circuit of claim 10, wherein a channel of the plurality of channels comprises:
 a reference insert circuit configured to insert a user-defined reference points at a predetermined position in the image data set; and   a reference point synchronization circuit configured to synchronize a first user-defined reference point of a first image data set with a second user-defined reference point of a second image data set.   
     
     
       12. The electronic circuit of claim 11, wherein the reference point synchronization circuit is further configured to perform a histogram calculation based on at least two inserted user-defined reference points. 
     
     
       13. The electronic circuit of claim 11, wherein the reference point synchronization circuit is field-programmable gate array. 
     
     
       14. The electronic circuit of claim 9, further comprising metallized traces configured to electrically connect electronic contacts of the plurality of ROICs to access leads of the respective layers of the stacked configuration. 
     
     
       15. The electronic circuit of claim 9, wherein the respective electrical connection disposed on the lateral surface of the stacked configuration is a T-connect structure. 
     
     
       16. The electronic circuit of claim 9, further comprising comparator circuitry configured to determine if the detector output signal is above or below a predetermined threshold. 
     
     
       17. The electronic circuit of claim 9, further comprising a storage circuit configured to store the image data set. 
     
     
       18. The electronic circuit of claim 17, wherein the storage circuit comprises a first-in, first-out (FIFO) shift register. 
     
     
       19. The electronic circuit of claim 17, wherein the storage circuit comprises a plurality of bin circuits, each bin circuit having a variable logic state and a unique position in the storage circuit. 
     
     
       20. The electronic circuit of claim 19, further comprising a reference insert circuit configured to assert a predetermined bin logic state in at least one of the plurality of bin circuits and to insert a reference point into the image data set. 
     
     
       21. The electronic circuit of claim 20, further comprising an output circuit configured to output the image data set. 
     
     
       22. The electronic circuit of claim 21, further comprising a reference point synchronization circuit configured to receive and synchronize digitalized data values of the outputted image data set using the inserted reference points. 
     
     
       23. The electronic circuit of claim 9, wherein the plurality of channels are defined upon one integrated circuit chip. 
     
     
       24. The electronic circuit of claim 9, wherein a first subset of the plurality of channels are defined upon a first integrated circuit chip, and wherein a second subset of the plurality of channels are defined upon a second integrated circuit chip. 
     
     
       25. A method comprising:
 converting received photons into a detector output signal using a photon detector array;   receiving and processing the detector output signal generated by the photon detector array at a first channel of a readout electronics integrated circuit (ROIC) of a processing module;   converting the output signal into an image data set at the first channel of the ROIC of the processing module, wherein the image data set includes a digital bit, wherein the ROIC is arranged in a stacked configuration with a plurality of other ROICs, and wherein the photon detector array is bonded to a lateral surface of the stacked configuration and is connected to each channel of a plurality of channels via a respective T-connect disposed on the lateral surface of the stacked configuration;   inserting a first user-defined reference point at a position in the image data set, wherein said inserting a first user-defined reference point includes asserting a predetermined bin logic state in a bit circuit of a storage circuit configured to store the image data set; and   synchronizing the first user-defined reference point with a second user-defined reference point associated with an integrated circuit layer of the processing module.   
     
     
       26. The method of claim 25, further comprising receiving photons reflected from a target. 
     
     
       27. The method of claim 25, further comprising performing a histogram calculation at a field-programmable gate array (FPGA) to determine positions of the first and second user-defined reference points and to define a realignment point for the image data set. 
     
     
       28. The method of claim 25, further comprising storing the image data set in the storage circuit. 
     
     
       29. The method of claim 28, wherein the storage circuit is a first-in, first-out (FIFO) shift register. 
     
     
       30. The method of claim 28, further comprising multiplexing the stored image data set to external processing circuitry. 
     
     
       31. The method of claim 25, further comprising determining via a comparator circuit if the detector output signal exceeds a predetermined threshold. 
     
     
       32. The method of claim 25, wherein said synchronizing comprises realigning the inserted first user-defined reference point with the second user-defined reference point to shift the image data set corresponding to the ROIC into alignment with another image data set corresponding to another ROIC of the plurality of other ROICs.