Layout technique for matched resistors on an integrated circuit substrate

Abstract

Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

1. A method for matching resistor impedances in an electrical a circuit configured for placement on an integrated circuit a substrate, the method comprising:
 determining desired resistor values to be associated with the circuit; and 
 defining interdigital structures to be formed across the substrate when the circuit is placed thereon, the interdigital structures being formed when independent paths of interconnected resistors split at one point on the substrate and recombine at another point, the independent paths of interconnected resistors being representative of the desired resistor values. 
 
     
     
       2. The apparatus method of  claim 1 , wherein the electrical circuit comprises a programmable gain amplifier (PGA). 
     
     
       3. The apparatus method of  claim 2 , wherein the PGA is a differential amplifier. 
     
     
       4. The apparatus method of  claim 3 , wherein the circuit is formed in CMOS. 
     
     
       5. An electrical network, comprising:
 a substrate; and   an interdigital structure formed on the substrate, the interdigital structure having independent paths of interconnected components, at least two of the independent paths meeting each other at at least two points, the independent paths of interconnected components being representative of a desired impedance value.   
     
     
       6. The electrical network of claim 5, wherein the interconnected components are resistors. 
     
     
       7. A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
 determining a desired impedance between the first node and the second node;   designing the electrical network to have a first component disposed in a first branch between the first node and the second node and to have a second component disposed in a second branch between the first node and the second node, the first and second branches being independent; and   arranging the first component and the second component in an interdigital pattern.   
     
     
       8. The method of claim 7, wherein the first component and the second component are resistors. 
     
     
       9. A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
 determining a desired impedance between the first node and the second node;   designing the electrical network to have a first component disposed in a first branch between the first node and a third node of the electrical network, a second component disposed in a second branch between the first node and the third node, a third component disposed in a third branch between the third node and the second node, and a fourth component disposed in a fourth branch between the third node and the second node, the first, second, third and fourth branches being independent;   arranging the first component and the second component in a first interdigital pattern; and   arranging the third component and the fourth component in a second interdigital pattern.   
     
     
       10. The method of claim 9, wherein the first component is a first resistor, the second component is a second resistor, the third component is a third resistor, and the fourth component is a fourth resistor. 
     
     
       11. The method of claim 9, wherein an impedance of the first component is substantially equal to an impedance of the second component. 
     
     
       12. The method of claim 9, wherein an impedance of the first component is substantially equal to an impedance of the third component. 
     
     
       13. The method of claim 9, wherein a length of the first branch is different from a length of the second branch. 
     
     
       14. The method of claim 9, wherein a length of the first branch is different from a length of the third branch. 
     
     
       15. The method of claim 9, wherein the first component comprises a first resistor and a second resistor. 
     
     
       16. The method of claim 15, wherein the first resistor is coupled in series to the second resistor. 
     
     
       17. The method of claim 15, wherein an impedance of the first resistor is substantially equal to an impedance of the second resistor. 
     
     
       18. An electrical network configured to minimize mismatch characteristics of impedances between a first node of the electrical network and a second node of the electrical network, comprising:
 a first component disposed in a first branch between the first node and the second node; and   a second component disposed in a second branch between the first node and the second node, the first and second branches being independent;   wherein the first component and the second component are arranged in an interdigital pattern and an impedance between the first node and the second node is a predetermined impedance.   
     
     
       19. The electrical network of claim 18, wherein the first component and the second component are resistors. 
     
     
       20. An electrical network configured to minimize mismatch characteristics of impedances between a first node of the electrical network and a second node of the electrical network, comprising:
 a first component disposed in a first branch between the first node and a third node of the electrical network;   a second component disposed in a second branch between the first node and the third node;   a third component disposed in a third branch between the third node and the second node; and   a fourth component disposed in a fourth branch between the third node and the second node, the first, second, third and fourth branches being independent;
 wherein an impedance between the first node and the second node is a predetermined impedance, and wherein the first component and the second component are arranged in a first interdigital pattern, and the third component and the fourth component are arranged in a second interdigital pattern. 
   
     
     
       21. The electrical network of claim 20, wherein the first component is a first resistor, the second component is a second resistor, the third component is a third resistor, and the fourth component is a fourth resistor. 
     
     
       22. The electrical network of claim 20, wherein an impedance of the first component is substantially equal to an impedance of the second component. 
     
     
       23. The electrical network of claim 20, wherein an impedance of the first component is substantially equal to an impedance of the third component. 
     
     
       24. The electrical network of claim 20, wherein a length of the first branch is different from a length of the second branch. 
     
     
       25. The electrical network of claim 20, wherein a length of the first branch is different from a length of the third branch. 
     
     
       26. The electrical network of claim 20, wherein the first component comprises a first resistor and a second resistor. 
     
     
       27. The electrical network of claim 26, wherein the first resistor is coupled in series to the second resistor. 
     
     
       28. The electrical network of claim 26, wherein an impedance of the first resistor is substantially equal to an impedance of the second resistor. 
     
     
       29. A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
 forming a first component disposed in a first branch between the first node and the second node; and   forming a second component disposed in a second branch between the first node and the second node, the first and second branches being independent;   wherein the first component and the second component are arranged in an interdigital pattern and an impedance between the first node and the second node is a predetermined impedance.   
     
     
       30. The method of claim 29, wherein the first component is a first resistor and the second component is a second resistor. 
     
     
       31. A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
 forming a first component disposed in a first branch between the first node and a third node of the electrical network;   forming a second component disposed in a second branch between the first node and the third node;   forming a third component disposed in a third branch between the third node and the second node; and   forming a fourth component disposed in a fourth branch between the third node and the second node, the first, second, third and fourth branches being independent;   wherein an impedance between the first node and the second node is a predetermined impedance, and wherein the first component and the second component are arranged in a first interdigital pattern, and the third component and the fourth component are arranged in a second interdigital pattern.   
     
     
       32. The method of claim 31, wherein the first component is a first resistor, the second component is a second resistor, the third component is a third resistor, and the fourth component is a fourth resistor.