Configurable cache allowing cache-type and buffer-type access

Abstract

A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache bit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

1. A memory storage system for storing recently accessed data from a main memory in a computer system, said memory storage system comprising:
 a memory storage area which is configurable into a cache portion and a buffer portion; and   means for storing indices corresponding to data stored in said memory storage area;   wherein when said cache portion is accessed by a given address, said index storage means is also accessed by said address to check if said data accessed from said cache portion is valid and when said buffer portion is accessed by said given address, said index storage means is not checked.   
     
     
       2. The memory system as described in  claim 1  wherein said index storage means further includes protection information indicating the access privilege of said given address into said main memory and when said index storage means is accessed by said given address, said protection information is concatenated onto an address accessed from said index storage means by said given address and provided to a CPU. 
     
     
       3. The memory system as described in  claim 2 , wherein said protection information includes a field that defines a coherence state of data stored at said given address, wherein said coherence state indicates whether data stored at said given address may be read, written into, or replaced. 
     
     
       4. The memory system as described in  claim 2  wherein said protection information includes a field that defines an access priority of said given address, wherein said access priority indicates the order at which said given address is accessed with respect to other accesses in said memory system. 
     
     
       5. The memory system as described in  claim 2  wherein said protection information includes a field for indicating when a detail exception should occur. 
     
     
       6. The memory system as described in  claim 2  wherein said protection information includes a field that defines a cache control condition of said given address, wherein said cache control condition indicates states of said data stored in said given address including a cache coherent state, a non-allocated state, and a physical state. 
     
     
       7. The memory system as described in  claim 1 , wherein said given address includes an indication of whether an access is being performed on at least one of said cache portion and said buffer portion. 
     
     
       8. A method for storing recently accessed data from a main memory in a computer system, comprising the steps of:
 configuring a memory storage area into a cache portion and a buffer portion; and   storing indices corresponding to data stored in said memory storage area;   wherein when said cache portion is accessed by a given address, said stored indices are also accessed by said given address to check if said data accessed from said cache portion is valid and when said buffer portion is accessed by said given address, said stored indices are not checked.   
     
     
       9. The method of  claim 8 , wherein said given address includes an indication of whether an access is being performed on at least one of said cache portion and said buffer portion. 
     
     
       10. The method of  claim 9 , wherein said protection information includes a field that defines a coherence state of data stored at said given address, wherein said coherence state indicates whether data stored at said given address may be read, written into, or replaced. 
     
     
       11. The method of  claim 9 , wherein said protection information includes a field that defines an access priority of said given address, wherein said access priority indicates the order at which said given address is accessed with respect to other accesses in said memory system. 
     
     
       12. The method of  claim 9 , wherein said protection information includes a field for indicating when a detail exception should occur. 
     
     
       13. The method of  claim 9 , wherein said protection information includes a field that defines a cache control condition of said given address, wherein said cache control condition indicates states of said data stored in said given address including a cache coherent state, a non-allocated state, and a physical state. 
     
     
       14. The method of  claim 8 , wherein said stored indices further include protection information indicating the access privilege of said given address into said main memory and when said stored indices are accessed by said given address, said protection information is concatenated onto an address accessed from said stored indices by said given address and provided to a CPU. 
     
     
       15. A computer-readable medium containing a program that performs the steps of:
 receiving an indication that a memory storage area has been configured into a cache portion and a buffer portion; and   storing indices corresponding to data stored in said memory storage area;   wherein when said cache portion is accessed by a given address, said stored indices are also accessed by said given address to check if said data accessed from said cache portion is valid and when said buffer portion is accessed by said given address, said stored indices are not checked.   
     
     
       16. The method of  claim 15 , wherein said given address includes an indication of whether an access is being performed on at least one of said cache portion and said buffer portion. 
     
     
       17. The computer-readable medium of  claim 16 , wherein said protection information includes a field that defines a coherence state of data stored at said given address, wherein said coherence state indicates whether data stored at said given address may be read, written into, or replaced. 
     
     
       18. The computer-readable medium of  claim 16 , wherein said protection information includes a field that defines an access priority of said given address, wherein said access priority indicates the order at which said given address is accessed with respect to other accesses in said memory system. 
     
     
       19. The computer-readable medium of  claim 16 , wherein said protection information includes a field for indicating when a detail exception should occur. 
     
     
       20. The computer-readable medium of  claim 16 , wherein said protection information includes a field that defines a cache control condition of said given address, wherein said cache control condition indicates states of said data stored in said given address including a cache coherent state, a non-allocated state, and a physical state. 
     
     
       21. The computer-readable medium of  claim 15 , wherein said stored indices further include protection information indicating the access privilege of said given address into said main memory and when said stored indices are accessed by said given address, said protection information is concatenated onto an address accessed from said stored indices by said given address and provided to a CPU. 
     
     
       22. A method of storing data accessed by a processor, the method comprising:
 receiving configuration information;   accessing a main memory;   partitioning a memory storage area into one of a predetermined number of combinations of a cache portion size and a buffer portion size in accordance with the received configuration information;   receiving an address within an address space divided into a cache address space portion and a buffer address space portion, wherein the address includes a field for indicating whether an access includes a cache access or a buffer access;   modifying at least a portion of the address using the configuration information, to produce a modified address; and   accessing data in said memory storage area by means of the modified address.   
     
     
       23. The method of claim 22 further comprising:
 if a cache miss is detected in an access to the cache portion, accessing the main memory for transferring data to or from the main memory,   wherein an access to the buffer portion does not result in an access to the main memory.   
     
     
       24. The method of claim 22 further comprising:
 storing indices corresponding to data stored in the memory storage area in a cache tag memory;   upon accessing the cache portion, checking the cache tag memory to determine whether the cache tag memory contains an index corresponding to the cache access; and   generating a cache hit if a corresponding index is found, and generating a cache miss if a corresponding index is not found.   
     
     
       25. The method of claim 22 wherein, in an access to the cache portion, the memory storage system determines whether an access to the main memory is required, and in an access to the buffer portion, no access to the main memory is required. 
     
     
       26. The method of claim 22 wherein buffer accesses have a fixed access time and cache accesses have a variable access time due to cache misses. 
     
     
       27. The method of claim 22, wherein an address bit in said address indicates whether the access is a cache access or a buffer access. 
     
     
       28. The method of claim 22 further comprising:
 partitioning the memory storage area between the cache portion and the buffer portion in accordance with configuration information received by the memory storage system.   
     
     
       29. The method of claim 22 further comprising:
 setting the configuration information in a status register when the computer system is configured by software.   
     
     
       30. The method of claim 22 further comprising:
 allocating address ranges to the cache portion and the buffer portion in accordance with the partitioning of the memory storage area between the cache portion and the buffer portion.   
     
     
       31. The method of claim 22 wherein the address space is divided into a cache address space portion and a buffer address space portion in accordance with at least the state of an address bit within the address space. 
     
     
       32. The method of claim 22 further comprising:
 delivering a portion of the address to the memory storage area without modification.   
     
     
       33. The method of claim 22 further comprising:
 delivering the modified address to the cache portion.   
     
     
       34. The method of claim 22 wherein the modified address is used to access the entire memory storage area for accesses within the buffer address space portion. 
     
     
       35. A method of storing data accessed by a processor, the method comprising:
 accessing a main memory;   receiving configuration information;   configuring a memory storage area into a cache portion and a buffer portion by partitioning the memory storage area between the cache portion and the buffer portion in accordance with the configuration information into one of a predetermined number of combinations of cache portion size and buffer portion size in accordance with configuration information received by the memory storage system;   receiving an address within an address space divided into a cache address space portion and a buffer address space portion;   modifying at least a portion of the address using the configuration information, to produce a modified address; and   accessing data in said memory storage area by means of an address that includes a field for indicating whether the access includes a cache access or a buffer access.   
     
     
       36. The method of claim 35 further comprising:
 delivering a portion of the address to the memory storage area without modification.   
     
     
       37. The method of claim 35 further comprising:
 delivering the modified address to the cache portion.   
     
     
       38. The method of claim 35 wherein the modified address is used to access the entire memory storage area for accesses within the buffer address space portion.