Liquid crystal driving circuit and liquid crystal display device

Abstract

As multiphase clocks to be supplied to a first gate driver that drives odd-numbered scanning lines in a liquid crystal display region and a second gate driver that drives even-numbered scanning lines, clocks, which are effective within an effective period of the image signal just before an image signal starts to be supplied to display elements for each scanning line of the liquid crystal display region, is generated and the first and second gate drivers drive switching elements in the effective period of the clock.

1. A liquid crystal driving circuit for a liquid crystal display device, the liquid crystal display device including: an active matrix-type liquid crystal display region; display elements formed in the liquid crystal display region; switching elements to perform switching to cause the display elements to hold an image signal, each of the switching elements including an amorphous silicon thin film transistor, said driving circuit comprising:
 a first gate driver that drives the switching element on odd-numbered scanning lines in the liquid crystal display region; 
 a second gate driver that drives the switching elements on even-numbered scanning lines in the liquid crystal display region; 
 a source driver that supplies source pulses as the image signal to the display elements via the corresponding switching elements, the source pulses having a first pulse width during which the image signal is active high; and 
 a clock generation circuit that generates multiphase clock signals in a form of clock pulses having a second pulse width, the clock signals being active high during the second pulse width, the clock signals being supplied to the first and second gate drivers, 
 wherein the multiphase clock signals become active high one first pulse width before the image signal to be supplied to the display elements becomes active high, a falling of the clock pulse being set within an active high period of the corresponding source pulse, and 
 the first and second gate drivers drive the switching elements in the active high period of the clock signals. 
 
     
     
       2. The liquid crystal driving circuit according to  claim 1 ,
 wherein the clock generation circuit generates a first clock pulse for controlling driving of the odd-numbered scanning lines in the liquid crystal display region and a second clock pulse for controlling driving of the even-numbered scanning lines, 
 the first gate driver starts to drive the switching elements based on the first clock pulse, and 
 the second gate driver starts to drive the switching elements based on the second clock pulse. 
 
     
     
       3. A liquid crystal display device, the liquid crystal display device including: an active matrix-type liquid crystal display region; display elements formed in the liquid crystal display region; switching elements to perform switching to cause the display elements to hold an image signal, each of the switching elements including an amorphous silicon thin film transistor, said liquid crystal display device comprising:
 a first gate driver that drives the switching element on odd-numbered scanning lines in the liquid crystal display region; 
 a second gate driver that drives the switching elements on even-numbered scanning lines in the liquid crystal display region; 
 a source driver that supplies source pulses as the image signal to the display elements via the corresponding switching elements, the source pulses having a first pulse width during which the image signal is active high; and 
 a clock generation circuit that generates multiphase clock signals in a form of clock pulses having a second pulse width, the clock signals being active high during the second pulse width, the clock signals being supplied to the first and second gate drivers, 
 wherein the multiphase clock signals become active high one first pulse width before the image signal to be supplied to the display elements becomes active high, a falling of the clock pulse being set within an active high period of the corresponding source pulse, and 
 the first and second gate drivers drive the switching elements in the active high period of the clock signals. 
 
     
     
       4. The liquid crystal display device according to  claim 3 ,
 wherein the clock generation circuit generates a first clock pulse for controlling driving of the odd-numbered scanning lines in the liquid crystal display region and a second clock pulse for controlling driving of the even-numbered scanning lines, 
 the first gate driver starts to drive the switching elements based on the first clock pulse, and 
 the second gate driver starts to drive the switching elements based on the second clock pulse. 
 
     
     
       5. A liquid crystal display comprising:
 a switching element configured to provide an image signal to a corresponding display element in a liquid crystal display region, wherein the corresponding display element is configured to hold the image signal provided by the switching element;   a gate driver configured to drive the switching element for a scanning line disposed in the liquid crystal display region to thereby provide the image signal to the corresponding display element;   a source driver configured to provide a source pulse as the image signal to the corresponding display element using the switching element, wherein the source pulse has a source pulse width throughout which the image signal is in an active state, and wherein the source driver is configured to provide a first source pulse throughout which a first image signal is in an active state and a second source pulse throughout which a second image signal is in an active state; and   a clock generation circuit configured to generate a clock pulse for the gate driver, wherein the clock pulse:
 has a clock pulse width that is greater than the source pulse width; and 
 goes to an active state at a start of the first source pulse and remains active until a middle of an active state of the second source pulse at which time the clock pulse goes to an inactive state; 
   wherein the gate driver is further configured to drive the switching element to an active state in response to the clock pulse and the second source pulse.   
     
     
       6. The liquid crystal display of claim 5, wherein the switching element comprises an amorphous silicon thin-film transistor. 
     
     
       7. The liquid crystal display of claim 6, wherein the gate driver comprises an amorphous silicon thin-film transistor. 
     
     
       8. The liquid crystal display of claim 5, wherein the clock generation circuit is further configured to generate multiphase clock signals. 
     
     
       9. The liquid crystal display of claim 5, configured such that the image signal of the source driver is at a high level during the active state. 
     
     
       10. The liquid crystal display of claim 5, configured such that the clock pulse is at a high level during the active state. 
     
     
       11. The liquid crystal display of claim 5, wherein the gate driver is further configured to drive odd-numbered scanning lines in the liquid crystal display region. 
     
     
       12. A liquid crystal display comprising:
 a switching element configured to provide an image signal to a corresponding display element in a liquid crystal display region, wherein the corresponding display element is configured to hold the image signal provided by the switching element;   a source driver configured to provide a source pulse as the image signal to the corresponding display element using the switching element, wherein the source pulse has a source pulse width throughout which the image signal is in an active state; and   a clock generation circuit configured to generate a clock pulse for use in clocking the source pulse as the image signal to the corresponding display element, wherein the clock pulse has a clock pulse width that is greater than the source pulse width, wherein the clock pulse begins one source pulse width before the image signal that is to be supplied to the corresponding display element goes to an active state, wherein the clock pulse goes to an inactive state at a middle of an active state of a subsequent source pulse, and wherein the source pulse is configured to be provided as the image signal upon transition of the clock pulse from an active state to an inactive state.   
     
     
       13. The liquid crystal display of claim 12, wherein the switching element comprises an amorphous silicon thin-film transistor. 
     
     
       14. The liquid crystal display of claim 12, wherein the clock generation circuit is further configured to generate multiphase clock signals. 
     
     
       15. The liquid crystal display of claim 12, configured such that the image signal of the source driver is at a high level during the active state. 
     
     
       16. The liquid crystal display of claim 12, configured such that the clock pulse is at a high level during the active state. 
     
     
       17. The liquid crystal display of claim 12, wherein the source driver is further configured to provide image signals on odd-numbered scanning lines in the liquid crystal display region. 
     
     
       18. A driving circuit for a liquid crystal display device, the liquid crystal display device having an active matrix-type liquid crystal display region with display elements and with switching elements configured to cause the display elements to hold an image signal, the liquid crystal driving circuit comprising:
 a gate driver configured to drive the switching elements for scanning lines in the liquid crystal display region;   a source driver configured to supply a source pulse as the image signal to a corresponding display element via a corresponding switching element, wherein the source pulse has a source pulse width throughout which the image signal is in an active state; and   a clock generation circuit configured to generate a clock signal including a clock pulse having a clock pulse width throughout which the clock signal is in an active state, wherein the clock pulse width is greater than the source pulse width, wherein the clock signal is configured to be provided to the gate driver, wherein the clock signal is further configured to go to an active state one source pulse width before the image signal that is to be provided to the corresponding display element by the clock signal goes to an active state, and wherein the clock pulse is configured to transition between the active state and an inactive state at a middle of an active state of an immediately subsequent source pulse to thereby provide the image signal to the corresponding display element.   
     
     
       19. The driving circuit of claim 18, wherein the switching element comprises an amorphous silicon thin-film transistor. 
     
     
       20. The driving circuit of claim 19, wherein the gate driver comprises an amorphous silicon thin-film transistor. 
     
     
       21. The driving circuit of claim 18, wherein the clock generation circuit is further configured to generate multiphase clock signals. 
     
     
       22. The driving circuit of claim 18, configured such that the image signal of the source driver is at a high level during the active state. 
     
     
       23. The driving circuit of claim 18, configured such that the clock pulse is at a high level during the active state. 
     
     
       24. The driving circuit of claim 18, wherein the gate driver is further configured to drive odd-numbered scanning lines in the liquid crystal display region.