Semiconductor device with a multilevel interconnection connected to a guard ring

Abstract

A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.

1. A semiconductor device comprising:
 a semiconductor chip; 
 a guard ring which is formed by part of an uppermost interconnection layer in a multilevel interconnection that is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers, the guard ring being arranged adjacent to each corner of the semiconductor chip; and 
 a conductive member which is buried in a contact hole formed in the low-permittivity insulating layer below the guard ring, and contacts the guard ring. 
 
     
     
       2. A device according to  claim 1 , wherein the guard ring is arranged along four sides of the semiconductor chip. 
     
     
       3. A device according to  claim 1 , wherein
 the conductive member includes plugs which are buried in contact holes formed in the respective insulating layers in the multilevel interconnection, and 
 the guard ring contacts a surface of the semiconductor chip via the plugs. 
 
     
     
       4. A device according to  claim 1 , wherein the conductive member is formed by part of an interconnection layer in the multilevel interconnection. 
     
     
       5. A device according to  claim 1 , further comprising a barrier film which is interposed between a low-permittivity insulating layer and an interconnection layer in the multilevel interconnection, and prevents oxidization and diffusion of the interconnection layer. 
     
     
       6. A device according to  claim 5 , wherein the barrier film includes an SiCN film. 
     
     
       7. A device according to  claim 1 , wherein the low-permittivity insulating layer has a relative dielectric constant of 3.0 to 2.5. 
     
     
       8. A device according to  claim 1 , wherein the guard ring has a width of not less than 10 μm. 
     
     
       9. A semiconductor device comprising:
 a substrate;   a plurality of interlayer dielectric films including a first interlayer dielectric film and a second interlayer dielectric film, the second interlayer dielectric film being formed below the first interlayer dielectric film, and two or more interlayer dielectric films having a pair of a low-k film and a barrier film;   a multilevel interconnection having a plurality of conductor layers;   a guard ring formed by a first part of an uppermost conductive layer in the multilevel interconnection, the guard ring being provided in the first interlayer dielectric film;   an alignment mark formed by a second part of an uppermost conductive layer in the multilevel interconnection, the alignment mark being provided in the first interlayer dielectric film;   a first contact portion provided below the guard ring in the first interlayer dielectric film, the first contact portion contacting the guard ring;   a first metal layer provided below the first contact portion in the second interlayer dielectric film, the first metal layer contacting the first contact portion; and   a second contact portion provided below the first metal layer in the second interlayer dielectric film, the second contact portion contacting the first metal layer.   
     
     
       10. A device according to claim 9, further comprising:
 a passive element and an active element formed on the semiconductor substrate.   
     
     
       11. A device according to claim 9, further comprising a plurality of third interlayer dielectric films stacked below the second interlayer dielectric film above the semiconductor substrate, a second metal layer and a third contact portion being provided in each of the third interlayer dielectric films, the third contact portion being provided below the second metal layer and contacting the second metal layer. 
     
     
       12. A device according to claim 11, wherein the guard ring is electrically connected to the substrate through second metal layers and third contact portions in third interlayer dielectric films. 
     
     
       13. A device according to claim 11, wherein the second metal layer and the third contact portion contain Cu and have a dual damascene structure. 
     
     
       14. A device according to claim 9, wherein the guard ring is arranged adjacent to a periphery of the semiconductor substrate. 
     
     
       15. A device according to claim 9, wherein a shape of the semiconductor substrate in a plane view is a rectangle, a plurality of alignment marks are formed at a plurality of corners of the substrate. 
     
     
       16. A device according to claim 9, wherein the low-k film includes an SiOC film and the barrier film includes an SiCN film. 
     
     
       17. A device according to claim 9, wherein the low-k film has a relative dielectric constant of 3.0 to 2.5. 
     
     
       18. A device according to claim 9, wherein the guard ring has a width of not less than 10 μm. 
     
     
       19. A device according to claim 9, further comprising:
 a passive element and an active element formed on the semiconductor substrate; and   a plurality of third interlayer dielectric films stacked below the second interlayer dielectric film above the semiconductor substrate, a second metal layer and a third contact portion being provided in each of third interlayer dielectric films, the third contact portion being provided below the second metal layer and contacting the second metal layer.   
     
     
       20. A device according to claim 19, further comprising:
 a first insulating film is formed between the semiconductor substrate and the lowest of the third interlayer dielectric films,   wherein the second metal layer provided in the lowest of the third interlayer dielectric films and is electrically connected to the passive element or the active element via a fourth contact layer provided in the first insulating film.   
     
     
       21. A device according to claim 20, wherein the first insulating film includes a BPSG film. 
     
     
       22. A device according to claim 20, wherein the fourth contact layer includes a W film. 
     
     
       23. A device according to claim 9, further comprising:
 a wiring layer provided in the first interlayer dielectric film; and   a bonding pad formed on the wiring layer.   
     
     
       24. A device according to claim 23, wherein the bonding pad includes an Al film. 
     
     
       25. A device according to claim 9, wherein the alignment mark is electrically connected to the substrate. 
     
     
       26. A semiconductor device comprising:
 a substrate;   a plurality of interlayer dielectric films including a first interlayer dielectric film and a second interlayer dielectric film, the second interlayer dielectric film being formed below the first interlayer dielectric film, two or more interlayer dielectric films having a pair of a low-k film and a barrier film;   a multilevel interconnection having a plurality of conductive layers;   an alignment mark formed by a first part of an uppermost conductive layer in the multilevel interconnection, the alignment mark being provided in the first interlayer dielectric film;   a guard ring formed by a second part of an uppermost conductive layer in the multilevel interconnection, the guard ring being provided in the first interlayer dielectric film and the guard ring surrounding the alignment mark;   a first contact portion provided below the guard ring in the first interlayer dielectric film, the first contact portion contacting the guard ring;   a first metal layer provided in the second interlayer dielectric film, the first metal layer contacting the first contact layer; and   a second contact portion provided in the second interlayer dielectric film, the second contact portion contacting the first metal layer.   
     
     
       27. A device according to claim 26, further comprising:
 a passive element and an active element formed on the substrate.   
     
     
       28. A device according to claim 26, further comprising a plurality of third interlayer dielectric films stacked below the second interlayer dielectric film above the substrate, a second metal layer and a third contact portion being provided in each of the third interlayer dielectric films, the third contact portion being provided below the second metal layer and contacting the second metal layer. 
     
     
       29. A device according to claim 28, wherein the guard ring is electrically connected to the substrate through second metal layers and third contact portions in third interlayer dielectric films. 
     
     
       30. A device according to claim 28, wherein the second metal layer and the third contact portion contain Cu and have a dual damascene structure. 
     
     
       31. A device according to claim 26, wherein a shape of the substrate in a plane view is a rectangle, a plurality of alignment marks are formed at a plurality of corners of the substrate. 
     
     
       32. A device according to claim 26, wherein the low-k film includes an SiOC film and the barrier film includes an SiCN film. 
     
     
       33. A device according to claim 26, wherein the low-k film has a relative dielectric constant of 3.0 to 2.5. 
     
     
       34. A device according to claim 26, wherein the guard ring has a width of not less than 10 μm. 
     
     
       35. A device according to claim 26, further comprising:
 a passive element and an active element formed on the substrate; and   a plurality of third interlayer dielectric films stacked below the second interlayer dielectric film above the substrate, a second metal layer and a third contact portion being provided in each of third interlayer dielectric films, the third contact portion being provided below the second metal layer and contacting the second metal layer.   
     
     
       36. A device according to claim 35, further comprising:
 a first insulating film is formed between the substrate and the lowest of the third interlayer dielectric films,   wherein the second metal layer provided in the lowest of the third interlayer dielectric films and is electrically connected to the passive element or the active element via a fourth contact layer provided in the first insulating film.   
     
     
       37. A device according to claim 36, wherein the first insulating film includes a BPSG film. 
     
     
       38. A device according to claim 36, wherein the fourth contact layer includes a W film. 
     
     
       39. A device according to claim 26, further comprising:
 a wiring layer provided in the first interlayer dielectric film; and   a bonding pad formed on the wiring layer.   
     
     
       40. A device according to claim 39, wherein the bonding pad includes an Al film. 
     
     
       41. A device according to claim 26, further comprising:
 another alignment mark provided in the second interlayer dielectric film or the third interlayer dielectric film.   
     
     
       42. A device according to claim 26, wherein the alignment mark is electrically connected to the substrate.