Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

1. A semiconductor integrated circuit comprising:
 a first branch line adapted to provide a potential to a first circuit cell, a power line being at said potential; 
 a second branch line adapted to provide said potential to a second circuit cell; and 
 a third branch line adapted to provide another potential to said first and second circuit cells, another power line being at said another potential, 
 wherein an electrical connection between said first branch line and said power line is controlled in accordance with a state of a control signal. 
 
     
     
       2. A semiconductor integrated circuit as set forth in  claim 1 , wherein said first circuit cell and said second circuit cell can be arranged mixed at any positions on said first and second branch lines. 
     
     
       3. A semiconductor integrated circuit as set forth in  claim 1 , wherein said potential is VSS. 
     
     
       4. A semiconductor integrated circuit as set forth in  claim 1 , wherein an interconnection between said power line and said second branch line is present regardless of said state of the control signal. 
     
     
       5. A semiconductor integrated circuit as set forth in  claim 1 , wherein said another potential is VDD. 
     
     
       6. A semiconductor integrated circuit as set forth in  claim 1 , wherein said third branch line connects said another power line to said first and second circuit cells regardless of said state of the control signal. 
     
     
       7. A semiconductor integrated circuit as set forth in  claim 1 , further comprising:
 a power switch cell adapted to control said electrical connection between said first branch line and said power line. 
 
     
     
       8. A semiconductor integrated circuit as set forth in  claim 7 , wherein said power switch cell comprises:
 a first interconnect line connected to said first branch line; 
 a second interconnect line connected to said power line; and 
 a switch circuit between said first interconnect line and said second interconnect line connecting said first interconnect line to said second interconnect line in accordance with said state of the control signal. 
 
     
     
       9. A semiconductor integrated circuit comprising:
 a power switch cell at an intersection of a group of power lines and a group of branch lines, said group of branch lines extending in a branch line direction and said group of power lines extending in a first power line direction;   an interconnect line electrically connecting one of the power lines in the group of power lines to one of the branch lines.   
     
     
       10. A semiconductor integrated circuit as set forth in claim 9, wherein said power switch cell is between two of the branch lines. 
     
     
       11. A semiconductor integrated circuit as set forth in claim 9, wherein said power switch cell is in an area, said area being under said group of power lines. 
     
     
       12. A semiconductor integrated circuit as set forth in claim 9, wherein said group of branch lines is in a lower layer, said group of power lines being in a layer other than said lower layer. 
     
     
       13. A semiconductor integrated circuit as set forth in claim 9, wherein said branch line direction is other than said first power line direction. 
     
     
       14. A semiconductor integrated circuit as set forth in claim 9, wherein said branch line direction is perpendicular to said first power line direction. 
     
     
       15. A semiconductor integrated circuit as set forth in claim 9, wherein said power switch cell is configured to control an electrical connection between said one of the branch lines and another of the branch lines. 
     
     
       16. A semiconductor integrated circuit as set forth in claim 15, wherein said power switch cell has a switch transistor, a source region of the switch transistor being electrically connected to said one of the branch lines. 
     
     
       17. A semiconductor integrated circuit as set forth in claim 16, wherein a drain region of the switch transistor is electrically connected to another of the branch lines. 
     
     
       18. A semiconductor integrated circuit as set forth in claim 16, wherein said electrical connection is controllable in accordance with a state of a control signal, a gate of said switch transistor being configured to receive said control signal. 
     
     
       19. A semiconductor integrated circuit as set forth in claim 16, wherein said switch transistor has a high threshold voltage. 
     
     
       20. A semiconductor integrated circuit as set forth in claim 16, wherein said transistor is electrically isolated from a different one of the branch lines. 
     
     
       21. A semiconductor integrated circuit as set forth in claim 20, further comprising:
 another interconnect line electrically connecting another of the power lines in the group of power lines to said different one of the branch lines.   
     
     
       22. A semiconductor integrated circuit as set forth in claim 20, wherein said different one of the branch lines is electrically connected to a substrate. 
     
     
       23. A semiconductor integrated circuit as set forth in claim 22, wherein said one of the branch lines is electrically connected to said substrate. 
     
     
       24. A semiconductor integrated circuit as set forth in claim 9, wherein said power switch cell has a plurality of transistors, a source/drain region for one of the transistors being electrically connected to said one of the branch lines or another of the branch lines. 
     
     
       25. A semiconductor integrated circuit as set forth in claim 24, wherein a source/drain region for another of the transistors is electrically connected to a different one of the branch lines. 
     
     
       26. A semiconductor integrated circuit as set forth in claim 9, further comprising:
 a first grouping of power lines extending linearly along said first power line direction, said group of power lines being included in said first grouping;   a second grouping of power lines extending linearly along a second power line direction, said second power line direction being other than said first power line direction,   wherein each group of power lines in said second grouping terminates at a power line group in the first grouping, each group of power lines in said first grouping terminating at a power line group in the second grouping.   
     
     
       27. A semiconductor integrated circuit as set forth in claim 26, wherein said power switch cell is between one of the power line groups in the first grouping and another of the power line groups in the first grouping. 
     
     
       28. A semiconductor integrated circuit as set forth in claim 26, wherein said power switch cell is between one of the power line groups in the second grouping and another of the power line groups in the second grouping. 
     
     
       29. A semiconductor integrated circuit as set forth in claim 26, wherein a different group of power lines is included in said second grouping, a power line in the different group of power lines being connected to said one of the power lines in the group of power lines. 
     
     
       30. A semiconductor integrated circuit as set forth in claim 29, wherein another power line in the different group of power lines being connected to another one of the power lines in the group of power lines. 
     
     
       31. A semiconductor integrated circuit as set forth in claim 26, wherein said first power line direction is perpendicular to said second power line direction. 
     
     
       32. A semiconductor integrated circuit as set forth in claim 26, wherein groups of power lines in said first grouping are arranged in parallel at substantially equal intervals. 
     
     
       33. A semiconductor integrated circuit as set forth in claim 26, wherein groups of power lines in said second grouping are arranged in parallel at substantially equal intervals. 
     
     
       34. A semiconductor integrated circuit as set forth in claim 26, wherein a power input cell is connected to a power line of said power line group in the first grouping, another power input cell being connected to a power line of said power line group in the second grouping. 
     
     
       35. A semiconductor integrated circuit as set forth in claim 34, wherein a power supply voltage from outside of the semiconductor integrated circuit is supplied to said power input cell, another power supply voltage from outside of said semiconductor integrated circuit being supplied to said another power input cell. 
     
     
       36. A semiconductor integrated circuit comprising:
 a plurality of circuit cells;   a plurality of group of power lines arranged in stripe shape;   a plurality of group of branch lines, said group of branch line branch out from said group of power line, and supplying power to at least one of said circuit cells; and   a power switch cell arranged in at least one of said group of branch lines, and turning on or off power supply to said circuit cells in accordance with a control signal,   wherein, at least part of said power switch cell is included in an area under said group of power lines, and said group of branch lines include a cross-hole connection line extending from a power line branch of said group of power lines to the under layer.