Balanced cells with fabrication mismatches that produce a unique number generator

Abstract

A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state, In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-random logic state when power is applied.

1. A semiconductor device comprising:
 a plurality of cells, wherein each cell is stable in a plurality of states, and wherein each cell includes a plurality of nodes, and wherein each cell is laid out to be a balanced cell with no preferred state, and wherein, after fabrication by a selected fabrication process, each cell includes variations caused by the inherent variability of the selected fabrication process such that, at power-up, each cell assumes one of the plurality of states as the variations cause the cell to become unbalanced, and wherein each cell includes: 
 a semiconductor region of a first conductivity type; 
 a well of a second conductivity type that touches the semiconductor region; 
 spaced-apart first source and first drain regions of the first conductivity type that touch the well; 
 a first channel region that lies between and contacts the first source and first drain regions; 
 spaced-apart first and second doped regions of the second conductivity type that touch the semiconductor region; 
 a second channel region that lies between and contacts the first and second doped regions; 
 ana first insulation region that touches the second channel region; 
 a first gate that touches the first insulation region, lies directly over the first channel region and the second channel region, and lies over the semiconductor region and well directly between the first source region and the first doped region, the first source region and the second doped region, the first drain region and the first doped region, and the first drain region and the second doped region, the first gate having a top surface and a pattern that defines a shape of the top surface; 
 spaced-apart second source and second drain regions of the first conductivity type that touch the well; 
 a third channel region that lies between and contacts the second source and second drain regions; 
 spaced-apart third and fourth doped regions of the second conductivity type that touch the semiconductor region; 
 a fourth channel region that lies between and contacts the third and fourth doped regions; 
 ana second insulation region that touches the fourth channel region; and 
 a second gate that touches the second insulation region that touches the fourth channel region, lies directly over the third channel region and the fourth channel region, and lies over the semiconductor region and well directly between the second source region and the third doped region, the second source region and the fourth doped region, the second drain region and the third doped region, and the second drain region and the fourth doped region, the second gate having a top surface and a pattern that defines a shape of the top surface of the second gate, the pattern of the first gate and the pattern of the second gate having symmetry; and 
 a control circuit including:
 a discharge control circuit configured to selectively output at least one signal that causes at least one of the plurality of nodes of at least one of the plurality of cells to be discharged; 
 a power control circuit configured to selectively output at least one signal that causes power to be applied to the cells following discharge of at least one of the plurality of nodes such that each cell assumes one of the plurality of states; and 
 a read circuit that reads the assumed states for at least a subset of the cells in the plurality of cells. 
 
 
     
     
       2. A semiconductor device comprising:
 a plurality of cells, wherein each cell is stable in a plurality of states, and wherein each cell includes a plurality of nodes, and wherein each cell is laid out to be a balanced cell with no preferred state, and wherein, after fabrication by a selected fabrication process, each cell includes variations caused by the inherent variability of the selected fabrication process such that, at power-up, each cell assumes one of the plurality of states as the variations cause the cell to become unbalanced, and wherein each cell includes:  
 a semiconductor region of a first conductivity type; 
 a well of a second conductivity type that touches the semiconductor region; 
 spaced-apart first source and first drain regions of the first conductivity type that touch the well; 
 a first channel region that lies between and contacts the first source and first drain regions; 
 spaced-apart first and second doped regions of the second conductivity type that touch the semiconductor region; 
 a second channel region that lies between and contacts the first and second doped regions; 
 ana first insulation region that touches the second channel region; 
 a first gate that touches the first insulation region, lies directly over the first channel region and the second channel region, and lies over the semiconductor region and well directly between the first source region and the first doped region, the first source region and the second doped region, the first drain region and the first doped region, and the first drain region and the second doped region, the first gate having a top surface and a pattern that defines a shape of the top surface; 
 spaced-apart second source and second drain regions of the first conductivity type that touch the well; 
 a third channel region that lies between and contacts the second source and second drain regions; 
 spaced-apart third and fourth doped regions of the second conductivity type that touch the semiconductor region; 
 a fourth channel region that lies between and contacts the third and fourth doped regions; 
 ana second insulation region that touches the fourth channel region; and 
 a second gate that touches the second insulation region that touches the fourth channel region, lies directly over the third channel region and the fourth channel region, and lies over the semiconductor region and well directly between the second source region and the third doped region, the second source region and the fourth doped region, the second drain region and the third doped region, and the second drain region and the fourth doped region, the second gate having a top surface and a pattern that defines a shape of the top surface of the second gate, the pattern of the first gate and the pattern of the second gate being substantially identical; and 
 a control circuit including:
 a discharge control circuit configured to selectively output at least one signal that causes at least one of the plurality of nodes of at least one of the plurality of cells to be discharged; 
 a power control circuit configured to selectively output at least one signal that causes power to be applied to the cells following discharge of at least one of the plurality of nodes such that each cell assumes one of the plurality of states; and 
 a read circuit that reads the assumed states for at least a subset of the cells in the plurality of cells. 
 
 
     
     
       3. The semiconductor device of  claim 2  wherein the first drain region lies a first distance from the second source region, and the second doped region lies the first distance from the third doped region. 
     
     
       4. The semiconductor device of  claim 3  wherein the first drain region lies a second distance from the second doped region, and the second drain region lies the second distance from the fourth doped region. 
     
     
       5. The semiconductor device of  claim 2  and further comprising:
 an isolation material that contacts the first and second gates, only the isolation material lying laterally between the first and second gates; and 
 a metal-1 trace that contacts the isolation material and lies over the first and second gates and a region that lies laterally between the first and second gates. 
 
     
     
       6. The semiconductor device of  claim 2  and further comprising a first metal-1 trace making an electrical connection with the first drain region and the second doped region, and a second metal-1 trace making an electrical connection with the second drain region and the fourth doped region. 
     
     
       7. The semiconductor device of  claim 6  and further comprising a first metal-2 trace making an electrical connection with the first metal-1 trace and the second gate, and a second metal-1 trace making an electrical connection with the second metal-1 trace and the first gate. 
     
     
       8. The semiconductor device of  claim 7  wherein the second metal-2 trace lies directly over the well and the first metal-2 trace lies directly over the semiconductor region, the first metal-2 trace not lying over the well. 
     
     
       9. The semiconductor device of  claim 2  and further comprising:
 a fifth doped region of the second conductivity type that touches the semiconductor region; 
 a fifth channel region that lies between and contacts the second doped region and the fifth doped region; 
 a sixth doped region of the second conductivity type that touches the semiconductor region; 
 a sixth channel region that lies between and contacts the fourth doped region and the sixth doped region; and 
 a third gate that lies directly over the fifth channel region and the sixth channel region. 
 
     
     
       10. The semiconductor device of  claim 9  and further comprising a first metal-1 trace making an electrical connection with the first drain region and the second doped region, a second metal-1 trace making an electrical connection with the second drain region and the fourth doped region, a third metal-1 trace making an electrical connection with the fifth doped region, and a fourth metal-1 trace making an electrical connection with the sixth doped region. 
     
     
       11. The semiconductor device of  claim 10  wherein the third and fourth metal-1 traces lie over the third gate. 
     
     
       12. The semiconductor device of  claim 11  and further comprising a first metal-2 trace making an electrical connection with the first metal-1 trace and the second gate, and a second metal-2 trace making an electrical connection with the second metal-1 trace and the first gate, the second metal-2 trace lying directly over the well, the first metal-2 trace lying directly over the semiconductor region, the first metal-2 trace not lying over the well. 
     
     
       13. The semiconductor device of  claim 12  wherein portions of the first and second gates lie between the well and the second metal-2 trace. 
     
     
       14. The semiconductor device of  claim 10  wherein the semiconductor device includes a plurality of cells arranged in rows and columns, each cell having a first side and a second side, the first side including the first gate, the first metal-1 trace, and the third metal-1 trace arranged in a first layout, the second side including the second gate, the second metal-1 trace, and the fourth metal-1 trace arranged in a second layout, the first layout and the second layout being identical. 
     
     
       15. The semiconductor device of  claim 14  wherein fabrication mismatches cause each cell to assume a non-random state. 
     
     
       16. The semiconductor device of  claim 2  wherein the semiconductor device includes a plurality of cells arranged in rows and columns, each cell having the first gate and the second gate. 
     
     
       17. The semiconductor device of  claim 16  wherein fabrication mismatches cause each cell to assume a non-random state. 
     
     
       18. The semiconductor device of  claim 6  wherein the semiconductor device includes a plurality of cells arranged in rows and columns, each cell having a first side and a second side, the first side including the first gate and the first metal-1 trace arranged in a first layout, the second side including the second gate and the second metal-1 trace arranged in a second layout, the first layout and the second layout being identical. 
     
     
       19. The semiconductor device of  claim 18  wherein fabrication mismatches cause each cell to assume a non-random state. 
     
     
       20. The semiconductor device of  claim 19  wherein the plurality of cells defines a non-deterministic number based on the non-random state of each cell. 
     
     
       21. A semiconductor device comprising:
 a plurality of cells, wherein each cell is stable in a plurality of states, and wherein each cell includes a plurality of nodes, and wherein each cell is laid out to be a balanced cell with no preferred state, and wherein, after fabrication by a selected fabrication process, each cell includes variations caused by the inherent variability of the selected fabrication process such that, at power-up, each cell assumes one of the plurality of states as the variations cause the cell to become unbalanced, and wherein each cell includes: 
 a semiconductor region of a first conductivity type; 
 a well of a second conductivity type that touches the semiconductor region; and 
 a group of semiconductor structures formed in a row to be identical, the group of semiconductor structures touching the semiconductor region and the well, each semiconductor structure in the row having:
 a first source region and a first drain region of the first conductivity type that touch the well; 
 a first channel region of the second conductivity type that lies between and touches the first source region and the first drain region; 
 a second source region and a second drain region of the second conductivity type that touch the semiconductor region; 
 a second channel region of the first conductivity type that lies between and touches the second source region and the second drain region; 
 a gate dielectric that touches the well over the first channel region and the semiconductor region over the second channel region; and 
 a gate that touches the gate dielectric, lies directly over the first channel region and the second channel region, and lies over the semiconductor region and well directly between the first source region and the second source region, the first source region and the second drain region, the first drain region and the second drain region, and the first drain region and the second source region; and 
 
 a control circuit including:
 a discharge control circuit configured to selectively output at least one signal that causes at least one of the plurality of nodes of at least one of the plurality of cells to be discharged; 
 a power control circuit configured to selectively output at least one signal that causes power to be applied to the cells following discharge of at least one of the plurality of nodes such that each cell assumes one of the plurality of states; and 
 a read circuit that reads the assumed states for at least a subset of the cells in the plurality of cells. 
 
 
     
     
       22. The semiconductor device of  claim 21  and further comprising:
 an isolation material that touches a top surface of each gate; and 
 a number of metal-1 segments formed to be identical that touch the isolation material, the number of metal-1 segments being formed so that a different metal-1 segment is formed over a portion of both gates of each adjacent pair of gates. 
 
     
     
       23. The semiconductor device of  claim 22  and further comprising a plurality of metal-1 traces formed to be identical that touch the isolation material, for each semiconductor structure, a metal-1 trace making an electrical connection with the first drain region and the second drain region of a semiconductor structure. 
     
     
       24. The semiconductor device of  claim 23  and further comprising:
 an insulation material that touches a top surface of each metal-1 segment and metal-1 trace; 
 a plurality of first metal-2 traces formed to be identical that touch the insulation material, a first metal-2 trace makes an electrical connection with the gate of the first semiconductor structure and a metal-1 trace electrically connected to the first and second drain regions of the second semiconductor structure; and 
 a plurality of second metal-2 traces formed to be identical that touch the insulation material, a second metal-2 trace makes an electrical connection with the gate of a second semiconductor structure that lies adjacent to the first semiconductor structure, and a metal-1 trace electrically connected to the first and second drain regions of the first semiconductor structure. 
 
     
     
       25. The semiconductor device of  claim 24  wherein the plurality of first metal-2 traces lie directly over the well and the plurality of second metal-2 traces lies directly over the semiconductor region, the plurality of second metal-2 traces not lying over the well. 
     
     
       26. The semiconductor device of claim 1, wherein the plurality of states are two states: logic high and logic low. 
     
     
       27. The semiconductor device of claim 26, wherein the plurality of cells is an array of cells. 
     
     
       28. The semiconductor device of claim 27, wherein the array of cells is included in a static random access memory (SRAM).