Apparatus and method for integrated circuit power management

Abstract

Methods and/or associated devices and/or systems for providing power management in electronic circuits, including custom ICs, programmable logic devices, and application specific integrated circuits (ASICs) places portions of various power management solutions in the I/O ring or in I/O macros. The invention has numerous specific embodiments and applications to a wide variety of ICs and logic or other circuit design components including circuit modules, software descriptions of circuit modules and/or design or simulation or test systems for circuit development.

1. A method of reducing power usage in an integrated circuit comprising:
 establishing separate power islands in said integrated circuit;, said power islands separating functional regions in a logic core of said integrated circuit to allow for separated power management of said separate functional regions;, said integrated circuit being of a type comprising an I/O ring surrounding said logic core; and  
 establishing one or more power control transistors in said I/O ring of said integrated circuit,;  
 using saidwherein said one or more power control transistors in said I/O ring are configured to control passage of power to one or more of said power-islands such that said power islands in said logic core;, thereby performing a multiplex function in said I/O ring, said multiplex function making available a plurality of different voltage levels for said islands; and, wherein said power islands are selectively disconnected from a power source by said power control transistors in said I/O ring, and wherein control for said multiplex function originates from a processor. 
 
     
     
       2. The method according to  claim 1  further comprising:
 providing a control signal generated externally to said one or more power control transistors to said transistors. 
 
     
     
       3. The method according to  claim 2  further wherein:
 said control signal is generated by logic located in said integrated circuit. 
 
     
     
       4. The method according to  claim 2  further wherein:
 said control signal is generated by logic located external to said integrated circuit. 
 
     
     
       5. The method according to  claim 1  further comprising:
 establishing a library of logic descriptions of power transistor I/O cells to allow use of said method with standard integrated circuit computer aided design tools. 
 
     
     
       6. The method according to  claim 1  further comprising:
 providing for multiple power inputs to a single power control transistor and/or multiple independently controlled power control transistors to a single power input. 
 
     
     
       7. The method according to  claim 2  further wherein:
 said control signal is overdriven. 
 
     
     
       8. The method according to  claim 1  further comprising:
 wherein said integrated circuit is a programmable logic device; 
 wherein said power islands provide power management for two or more different programmable areas of said programmable logic device. 
 
     
     
       9. The method according to  claim 1  further comprising:
 integrating electrostatic discharge protection into circuitry enabling said separate power islands. 
 
     
     
       10. The method according to  claim 1  further comprising:
 configuring a selector in said I/O ring, said selector making available a plurality of different voltage levels for said islands. 
 
     
     
       11. The method according to  claim 10  further wherein said selector can be placed according to a placement strategy selected from the group consisting of:
 corner placement, 
 expansion of I/O ring size; and 
 increasing height of I/O cells. 
 
     
     
       12. The method according to  claim 1  further wherein:
 using one or more of said power control transistors to provide of said multiplex function to said power control transistors located in said I/O ring. 
 
     
     
       13. The method according to  claim 12  further wherein:
 at least one of said inputs to said multiplexing function is the output of a power control transistor input of which is the output of a voltage reduction circuit also located in said I/O ring. 
 
     
     
       14. The method according to  claim 10  further wherein:
 said multiplexing function is performed in said I/O ring, so that it is transparent to said power island. 
 
     
     
       15. The method according to  claim 1  further wherein:
 controls for said transistors are configured such that either one or none will allow passage of power to said power-island, thus providing at least three different power levels to the power-island: VDD 1 , VDD 2  or 0V. 
 
     
     
       16. The method according to  claim 1  further comprising:
 placing one or more voltage reduction circuits between said power source and said one or more power control transistors allowing for different virtual power levels to be delivered to said I/C core. 
 
     
     
       17. The method according to  claim 1  further wherein:
 said power control transistors can be placed according to a placement strategy selected from the group consisting of: 
 corner placement; 
 expansion of I/O ring size; and 
 increasing height of I/O cells. 
 
     
     
       18. An information appliance with one or more advanced power control components operated in accordance with the method of  claim 1 . 
     
     
       19. An integrated circuit fabrication wafer containing circuitry that when active includes logic operated in accordance with the method of  claim 1 . 
     
     
       20. A computer readable medium containing computer interpretable instructions that when loaded into an appropriately configuration information processing device will cause the device to operate in accordance with the method of  claim 1  in an emulation system. 
     
     
       21. An integrated circuit device having power management comprising:
 a logic core roughly centrally configured on an integrated circuit device, said logic core comprising a large plurality of logic circuits; 
 one or more power supply inputs, said power supply inputs providing voltage and or current energy for operating said logic core; 
 an I/O ring roughly surrounding said logic core, said I/O ring providing connections and support circuitry for connecting said logic core to one or more external connections; and 
 aat least one power control transistor in said I/O ring, said power control transistor providing the ability to vary power levels to islands of logic circuits within said logic core, wherein said logic core and said I/O ring including said power control transistors are circuits integrated on a single integrateintegrated circuit device, said device connected to other logic through external transmission connections to a plurality of bond pads;, thereby performing a multiplex function in said I/O ring, said multiplex function making available a plurality of different voltage levels for said islands. 
 
     
     
       22. The device according to  claim 21  further comprising:
 power controller circuitry with-in said logic core, said power control circuitry generating one or more signals controlling said power control transistors. 
 
     
     
       23. A computer readable medium containing computer interpretable instructions describing a circuit layout for an integrated circuit that, when constructed according to said descriptions, will configure a circuit to embody the apparatus described in  claim 21 . 
     
     
       24. An integrated circuit, comprising:
 a logic core including a plurality of logic circuits; and   an input/output (I/O) ring structure coupled to the logic core and configured as a ring that roughly surrounds the logic core, wherein the I/O ring structure includes:
 connectors and support circuitry configured to facilitate connection of the logic core to one or more external components; and 
 at least one power gating circuit that includes at least one power control transistor and is configured to perform a multiplex function in a group of one or more of the plurality of logic circuits, wherein the multiplex function includes control of passage of power to the group of one or more of the plurality of logic circuits, and wherein the multiplex function makes a plurality of different supply voltage levels available to the group of one or more of the plurality of logic circuits. 
   
     
     
       25. The integrated circuit of claim 24, wherein the I/O ring structure further comprises a core power I/O component coupled to the power gating circuit, and wherein the core power I/O component is configured to provide power to the power gating circuit. 
     
     
       26. The integrated circuit of claim 25, wherein the core power I/O component is further configured to provide non-gated power to at least another portion of the logic core. 
     
     
       27. The integrated circuit of claim 24, further comprising a bond pad coupled to the I/O ring structure. 
     
     
       28. The integrated circuit of claim 24, wherein the integrated circuit comprises a field programmable gate array. 
     
     
       29. The integrated circuit of claim 24, further comprising a power control unit coupled to the I/O ring structure, wherein the power control unit is configured to generate one or more power gating circuit control signals. 
     
     
       30. The integrated circuit of claim 24, wherein the logic core comprises a power input configured to accept a connection from the at least one power gating circuit. 
     
     
       31. The integrated circuit of claim 24, wherein the at least one power gating circuit comprises a plurality of power gating transistors each coupled to a corresponding one of the plurality of different supply voltage levels, wherein the plurality of different supply voltage levels includes at least two non-zero supply voltage levels, and wherein the at least one power gating circuit is configured to select one of the plurality of power gating transistors to vary the power level. 
     
     
       32. The integrated circuit of claim 31, wherein the at least one power gating circuit is further configured to select one of the plurality of power gating transistors based on a received control signal. 
     
     
       33. The integrated circuit of claim 24, further comprising a voltage reduction circuit coupled to a nominal power supply input and to the at least one power gating circuit. 
     
     
       34. The integrated circuit of claim 24, wherein the at least one power gating circuit is positioned in a corner location of the integrated circuit. 
     
     
       35. A method, comprising:
 operating logic circuits in power islands of an integrated circuit that are connected to one or more components external to the integrated circuit; and   controlling passage of power to the different ones of the logic circuits by one or more power gating circuits in an I/O ring of the integrated circuit, wherein the one or more power gating circuits in the I/O ring include one or more power control transistors, wherein said controlling includes selective disconnection of power to the logic circuits, wherein the one or more power gating circuits are configured to perform a multiplex function including making available different voltage supply levels for different ones of the logic circuits of the power islands, and wherein control for the multiplex function originates from a processor.   
     
     
       36. The method of claim 35, further comprising providing, by a control circuit, a control signal to the one or more power control transistors of the one or more power gating circuits. 
     
     
       37. The method of claim 35, wherein the integrated circuit comprises a programmable logic device, and wherein the plurality of logic circuits of the power islands correspond to programmable areas of the programmable logic device. 
     
     
       38. The method of claim 35, wherein the different voltage levels comprise at least two non-zero voltage levels. 
     
     
       39. The method of claim 35, further comprising positioning the one or more power gating circuits at one or more locations of the integrated circuit according to a placement strategy selected from the group consisting of:
 a corner placement;   expansion of I/O ring size; and   increasing height of I/O cells.   
     
     
       40. The method of claim 35, further comprising positioning one or more voltage reduction circuits between a power source and the one or more power gating circuits. 
     
     
       41. An article of manufacture, comprising:
 a non-transitory, computer-readable medium; and   a plurality of programming instructions stored on the non-transitory, computer-readable medium and configured to, upon execution by a processor of a computing device, cause the computing device to:
 establish logic circuits in power islands of an integrated circuit that are to be connected to one or more components external to the integrated circuit; and 
 establish one or more power gating circuits in an I/O ring of the integrated circuit, wherein the one or more power gating circuits in the I/O ring include one or more power transistors and are configured to control passage of power to the different ones of the logic circuits, including selective disconnection of power to the logic circuits, wherein the one or more power gating circuits are further configured to perform a multiplex function, and wherein the multiplex function includes making available different voltage supply levels for different ones of the logic circuits of the power islands. 
   
     
     
       42. The article of claim 41, wherein the plurality of programming instructions are further configured to, upon execution by the processor, cause the computing device to establish a control circuit configured to provide a control signal to the one or more power control transistors of the one or more power gating circuits. 
     
     
       43. The article of claim 41, wherein the plurality of programming instructions are further configured to cause, upon execution by the processor, the computing device to position the one or more power gating circuits at one or more locations of the integrated circuit according to a placement strategy selected from the group consisting of:
 a corner placement;   expansion of I/O ring size; and   an increase in a height of I/O cells.   
     
     
       44. The article of claim 41, wherein the plurality of programming instructions are further configured to cause, upon execution by the processor, the computing device to position one or more voltage reduction circuits between a power source and the one or more power gating circuits.