Data bus line control circuit

Abstract

A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.

1. A data bus line control circuit, comprising:
 atwo pairs of global data bus line which islines arranged between adjacent memory units adjacent to each other as two pairs, and transmits atransmitting data from a plurality of local data bus linelines positioned between adjacent sub blocks; and 
 transmission means which is connected between the local data bus line lines and the global data bus line, and transmits lines transmitting in a first mode of operation bit line signals of two sub blocks, amplified by a plurality of bit line sense-amp sense-amps, to one pair both pairs of global data bus lines different from each other through the local data bus line lines, when the two sub blocks are simultaneously selected by a block isolation selection signal signal, and transmitting in a second mode of operation bit line signals of one sub block, amplified by a plurality of bit line sense-amps, to at least one pair of the global data bus lines through local data bus lines, when the one sub block is selected by the block isolation selection signal. 
 
     
     
       2. A data bus line control circuit according to  claim 1 , wherein: a block isolation selection signal of a sub block adjacent to the selected sub blocks becomes inactivated, and a block isolation selection signal of a sub block not adjacent to the selected sub block blocks becomes activated. 
     
     
       3. A data bus line control circuit according to  claim 1 , wherein:
 the transmission means is controlled by a signal of inverting the block isolation selection signal. 
 
     
     
       4. A data bus line control circuit according to  claim 3 , wherein:
 the transmission means is comprised of a plurality of metal-oxide semiconductor (MOS) elements of which gate terminals receive the inverted block isolation selection signal as an input. 
 
     
     
       5. A data bus line control circuit according to claim 1, wherein: the first and second modes of operation are refresh operations. 
     
     
       6. A data bus line control circuit according to claim 5, wherein: the first mode of operation has half a number of refresh cycles of the second mode of operation. 
     
     
       7. A data bus line control circuit according to claim 6, wherein: the first mode of operation has 4k refresh cycles and the second mode of operation has 8k refresh cycles. 
     
     
       8. A data bus line control circuit according to claim 1, wherein: the transmission means is comprised of a plurality of NMOS transistors. 
     
     
       9. A data bus line control circuit according to claim 8, wherein: the block isolation selection signals have a Vss level when inactive and a Vpp level when active. 
     
     
       10. A data bus line control circuit according to claim 8, wherein: the block isolation selection signals have a Vss level when inactive and a Vpp level when active.