Impedance blocking filter circuit

Abstract

An impedance blocking filter circuit is provided for use in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. The filter circuit includes first, second, and third inductors connected in series between a first input terminal and a first common point. A first resistor has its one end connected also to the first common point and its other end connected to a first output terminal. Fourth, fifth and sixth inductors are connected in series between a second input terminal and a second common point. A second resistor has its one end also connected to the second common point and its other end connected to a second output terminal. A capacitor has its ends connected across the first and second common points. In another aspect, the filter circuit also includes current limiting protection circuitry for reducing ring trip, dial pulse and off-hook transient current spikes.

1. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances from above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit, said filter circuit comprising:
 first, second, and third inductors connected in series between a first input terminal and a first common point;   said first inductor having its one end connected to said first input terminal and its other end connected to one end of said second inductor, said second inductor having its other end connected to one end of said third inductor, said third inductor having its other end connected to said first common point;   a first resistor having its one end also connected to said first common point and its other end connected to a first output terminal;   fourth, fifth, and sixth inductors connected in series between a second input terminal and a second common point;   said four inductor having its one end connected to said second input terminal and its other end connected to one end of said fifth inductor, said fifth inductor having its other end connected to one end of said sixth inductor, said sixth inductor having its other end connected to said second common point;   a second resistor having its one end also connected to said second common point and its other end connected to a second output terminal; and   a capacitor having its one end connected to said first common point and its other end connected to said second common point.   
     
     
       2. An impedance blocking filter circuit as claimed in  claim 1 , wherein said first and fourth inductors are comprised of ferrite toroids. 
     
     
       3. An impedance blocking filter circuit as claimed in  claim 2 , wherein said second and fifth inductors have values on the order of 220 μH. 
     
     
       4. An impedance blocking filter circuit as claimed in  claim 3 , wherein said third and sixth inductors have values on the order of 10 mH. 
     
     
       5. An impedance blocking filter circuit as claimed in  claim 4 , wherein said first and second resistors have values on the order of 22 Ohms. 
     
     
       6. An impedance blocking filter circuit as claimed in  claim 5 , wherein said capacitor has the value on the order of 22 nf. 
     
     
       7. An impedance blocking filter circuit as claimed in  claim 1 , further comprising current limiting protection means connected between said common points and said output terminals for reducing current spikes caused by the customer's terminal equipment going off-hook. 
     
     
       8. An impedance blocking filter circuit as claimed in  claim 7 , wherein said current limiting protection means is comprised of first and second depletion mode field-effect transistors and first and second transient protection varistors. 
     
     
       9. An impedance blocking filter circuit as claimed in  claim 8 , wherein said first depletion mode field-effect transistor has its conduction path electrodes interconnected between said first common point and said one end of said first resistor and its gate electrode connected to said other end of said first resistor, said second depletion mode field-effect transistor having its conduction path electrodes interconnected between said second common point and said one end of said second resistor and its gate electrode connected to said other end of said second resistor, said first varistor having its one end connected also to said first common point and its other end connected to said first output terminal, said second varistor having its one end connected also to said second common point and its other end connected to said second output terminal. 
     
     
       10. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances from above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit, said filter circuit comprising:
 first, second, and third inductors connected in series between a first input terminal and a first common point;   said first inductor having its one end connected to said first input terminal and its other end connected to one end of said second inductor, said second inductor having its other end connected to one end of said third inductor, said third inductor having its other end connected to said first common point;   a seventh inductor and a first resistor connected in series between said first common point and a first output terminal, said seventh inductor having its one end connected also to said first common point and its other end connected to one end of said first resistor, said first resistor having its other end connected to a first output terminal;   fourth, fifth, and sixth inductors connected in series between a second input terminal and a second common point;   said four inductor having its one end connected to said second input terminal and its other end connected to one end of said fifth inductor, said fifth inductor having its other end connected to one end of said sixth inductor, said sixth inductor having its other end connected to said second common point;   an eighth inductor and a second resistor connected in series between said second common point and a second output terminal, said eighth inductor having its one end connected also to said second common point and its other end connected to one end of said second resistor, said second resistor having its other end connected to a second output terminal; and   a capacitor having its one end connected to said first common point and its other end connected to said second common point.   
     
     
       11. An impedance blocking filter circuit as claimed in  claim 10 , wherein said first and fourth inductors are comprised of ferrite toroids. 
     
     
       12. An impedance blocking filter circuit as claimed in  claim 11 , wherein said second and fifth inductors have values on the order of 220 μH. 
     
     
       13. An impedance blocking filter circuit as claimed in  claim 12 , wherein said third and sixth inductors have values on the order of 5-10 mH. 
     
     
       14. An impedance blocking filter circuit as claimed in  claim 13 , wherein said seventh and eighth inductors have values on the order of 5-10 mH. 
     
     
       15. An impedance blocking filter circuit as claimed in  claim 14 , wherein said first and second resistors have values on the order of 22 Ohms. 
     
     
       16. An impedance blocking filter circuit as claimed in  claim 15 , wherein said capacitor has the value on the order of 47 nf. 
     
     
       17. An impedance blocking filter circuit as claimed in  claim 1 , further comprising home network demarcation filter means interconnected between the incoming telephone lines and internal house wiring for blocking the impedance of the customer's terminal equipment from home networking signals. 
     
     
       18. An impedance blocking filter circuit as claimed in  claim 17 , said demarcation filter means is comprised of six inductors and two capacitors. 
     
     
       19. An impedance blocking filter circuit as claimed in  claim 10 , further comprising home network demarcation filter means interconnected between the incoming telephone lines and internal house wiring for blocking the impedance of the customer's terminal equipment from home networking signals. 
     
     
       20. An impedance blocking filter circuit as claimed in  claim 19 , said demarcation filter means is comprised of six inductors and two capacitors. 
     
     
       21. A telecommunications filter, comprising:
 at least three first inductors electrically disposed between a first input terminal of an incoming telephone line and a first common point;   at least three second inductors electrically disposed between a second input terminal of an incoming telephone line and a second common point;   at least one capacitor disposed electrically between said first and second common points; and   a current limiting protection circuit disposed electrically between said first and second common points and respective ones of a first output terminal and a second output terminal.   
     
     
       22. The filter of claim 21, wherein said filter comprises a high-frequency impedance blocking capability with the capability to block impedances above approximately 20 kHz. 
     
     
       23. The filter of claim 21, wherein at least one of each of said three first inductors and said three second inductors comprises a ferrite toroid. 
     
     
       24. The filter of claim 23, wherein at least one of each of said three first and second inductors has an inductance value on the order of 220 μH. 
     
     
       25. The filter of claim 24, wherein at least one of each of said three first and second inductors has an inductance value on the order of 10 mH. 
     
     
       26. The filter of claim 21, wherein said current limiting protection circuit comprises first and second resistors each have a resistance value on the order of 5-20 Ohms. 
     
     
       27. The filter of claim 26, wherein at least one of each of said three first and second inductors comprises a ferrite toroid. 
     
     
       28. The filter of claim 27, wherein at least one of each of said three first and second inductors has an inductance value on the order of 220 μH. 
     
     
       29. The filter of claim 28, wherein at least one of each of said three first and second inductors has an inductance value on the order of 5 mH. 
     
     
       30. The filter of claim 29, wherein said at least one third and fourth inductors each has an inductance value on the order of 5 mH. 
     
     
       31. The filter of claim 21, wherein said at least one capacitor has a capacitance value on the order of 22 nf. 
     
     
       32. The filter of claim 21, wherein said filter is adapted for interconnection between incoming telephone lines and a customer's terminal equipment and configured so as to unconditionally block impedances from above 20 KHz associated with the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. 
     
     
       33. A telecommunications filter circuit comprising:
 at least one first inductor electrically disposed between a first input terminal of an incoming telephone line and a first common point;   at least one second inductor electrically disposed between a second input terminal of an incoming telephone line and a second common point;   at least one capacitor disposed electrically between said first and second common points; and   a substantially transistorized current limiter disposed between said first and second common points and a first output terminal and a second output terminal.   
     
     
       34. The filter circuit of claim 33, wherein said current limiter is adapted to reduce current spikes caused by terminal equipment coupled to said output terminals going off-hook. 
     
     
       35. The filter circuit of claim 33, wherein said current limiter comprises first and second field-effect transistors and first and second varistors. 
     
     
       36. The filter circuit of claim 33, further comprising:
 at least one third inductor disposed electrically between said first common point and said current limiter; and   at least one fourth inductor disposed electrically between said second common point and said current limiter.   
     
     
       37. An impedance blocking DSL filter circuit, comprising:
 a plurality of first input terminals from an incoming telephone line;   a plurality of second output terminals;   a plurality of common points disposed electrically between respective ones of said first input terminals and said second output terminals;   a first filter stage disposed electrically between said first input terminals and said common points;   a second filter stage disposed electrically between said common points and said second output terminals, said second stage comprising at least one substantially transistorized current limiter; and   a capacitance disposed electrically between said common points.   
     
     
       38. A telecommunications filter circuit comprising:
 at least one first inductor electrically disposed between a first input terminal and a first common point;   at least one second inductor electrically disposed between a second input terminal and a second common point;   at least one capacitor disposed electrically between said first and second common points; and   a substantially transistorized current limiter comprising first and second field-effect transistors and first and second varistors and first and second resistors, said first field-effect transistor having its conduction path electrodes interconnected between said first common point and a first end of said first resistor and its gate electrode connected to a second end of said first resistor, said second field-effect transistor having its conduction path electrodes interconnected between said second common point and a first end of said second resistor and its gate electrode connected to a second end of said second resistor, said first varistor having its one end connected also to said first common point and its other end connected to said first output terminal, said second varistor having its one end connected also to said second common point and its other end connected to said second output terminal.