Universal input apparatus

Abstract

Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.

What is claimed is: 
     
       1. A method for coupling an input signal to a circuit, said method comprising
 receiving an input signal according to a first voltage standard; 
 establishing a circuit input voltage proportional to the voltage of said Input input signal using a voltage divider; and 
 coupling a center tap pin to a reference node, thereby terminating said input signal, wherein said reference node is chosen based on said first voltage standard. 
 
     
     
       2. A method according to  claim 1 , wherein said first voltage standard is CML, and said reference node is an open, or not connected, node. 
     
     
       3. A method according to  claim 1 , wherein said first voltage standard is CML, said input signal is AC-coupled to said circuit, and said reference node is an AC reference node. 
     
     
       4. A method according to  claim 1 , wherein said first voltage standard is PECL, and said reference node has a voltage (VCC−2V). 
     
     
       5. A method according to  claim 1 , wherein said first voltage standard is PECL, said input signal is AC-coupled to said circuit, and said reference node is an AC reference node. 
     
     
       6. A method according to  claim 1 , wherein said first voltage standard is LVDS, and said reference node is an open, or not connected, node. 
     
     
       7. A method according to  claim 1 , wherein said first voltage standard is HSTL and said reference node is a ground node. 
     
     
       8. A method for coupling a differential output signal according to a first logic standard to a circuit, said method comprising:
 providing an integrated circuit comprising:
 a first voltage divider having a first intermediate node and a second voltage divider having a second intermediate node; and 
 a termination pair comprising first and second resistors, wherein said first resistor 
 
 is coupled to said first voltage divider and said second resistor is coupled to said second voltage divider; and a center pin coupled to said first and second resistors; 
 coupling said differential output signal to said first and second intermediate nodes; and 
 coupling said center pin to a reference node, wherein the voltage at said reference node is chosen based on said logic standard. 
 
     
     
       9. A method according to  claim 8 , wherein said first logic standard is CML and said reference node is an open, or not connected, reference node. 
     
     
       10. A method according to  claim 8 , wherein said first logic standard is CML, said differential output signal is AC-coupled to said first and second voltage dividers, and said reference node comprises an AC reference node. 
     
     
       11. A method according to  claim 8 , wherein said first logic standard is PECL, and said reference node comprises a node having a voltage (VCC−2V). 
     
     
       12. A method according to  claim 8 , wherein said first logic standard is PECL, said differential output signal is AC coupled to said first and second voltage dividers, and said reference node comprises an AC reference node. 
     
     
       13. A method according to  claim 8 , wherein said first logic standard is LVDS and said reference node is an open, or not connected, reference node. 
     
     
       14. A method according to  claim 8 , wherein said first logic standard is HSTL and said reference node is a ground node. 
     
     
       15. A method according to  claim 8 , wherein said first and second resistors are 50Ω resistors. 
     
     
       16. A packaged integrated circuit according to  claim 8 , wherein said first and second resistors are 50Ω resistors. 
     
     
       17. A packaged integrated circuit comprising:
 an integrated circuit comprising:
 a first voltage divider having a first intermediate node and a second voltage divider having a second intermediate node; and 
 a termination pair comprising first and second resistors, wherein said first resistor is coupled to said first voltage divider and said second resistor is coupled to said second voltage divider; and 
 
 a package comprising said integrated circuit and 
 a first input pin coupled to said first voltage divider; 
 a second input pin coupled to said second voltage divider; and 
 a third input pin coupled to said first and second resistors. 
 
     
     
       18. A method for coupling an input signal to a circuit, said method comprising
 receiving the input signal according to a first voltage standard, the input signal being a differential input signal comprising an inverted input signal and a non-inverted input signal, the inverted input signal being applied to a first pin of an integrated circuit package, and the non-inverted signal being applied to a second pin of the integrated circuit package;   coupling a third pin of the integrated circuit package, acting as a center tap pin, to a reference node, thereby terminating said input signal, wherein said reference node is chosen based on said first voltage standard, the third pin being connected within the integrated circuit package to the first pin by a first termination resistance, the third pin also being connected within the integrated circuit package to the second pin by a second termination resistance,   wherein the third pin is directly connected to a junction between the first termination resistance and the second termination resistance such that there is no additional resistance between the third pin and the junction;   amplifying the input signal by a differential amplifier internal to the integrated circuit package;   outputting an output signal, controlled by the input signal, on at least a fourth pin of the integrated circuit package; and   providing at a fifth pin of the integrated circuit package a reference voltage generated internal to the integrated circuit package, the fifth pin for being connected to the third pin as a reference voltage for AC coupled input signals.   
     
     
       19. A method according to claim 18, wherein said first voltage standard is CML, and said reference node is an open, or not connected, node. 
     
     
       20. A method according to claim 18, wherein said first voltage standard is CML, said input signal is AC-coupled to said circuit, and said reference node is an AC reference node. 
     
     
       21. A method according to claim 18, wherein said first voltage standard is PECL, and said reference node has a voltage (VCC-2V). 
     
     
       22. A method according to claim 18, wherein said first voltage standard is PECL, said input signal is AC-coupled to said circuit, and said reference node is an AC reference node. 
     
     
       23. A method according to claim 18, wherein said first voltage standard is LVDS, and said reference node is an open, or not connected, node. 
     
     
       24. A method according to claim 18, wherein said first voltage standard is HSTL and said reference node is a ground node. 
     
     
       25. A method according to claim 18 wherein the reference voltage generated at the fifth pin is nominally a supply voltage (Vcc) minus 1.4 volts. 
     
     
       26. A method according to claim 18 wherein the first termination resistance is 50Ω, and the second termination resistance is 50Ω. 
     
     
       27. A method according to claim 26 where the first termination resistance and the second termination resistance are resistors. 
     
     
       28. A structure comprising an integrated circuit encased in an integrated circuit package, the structure comprising:
 a first pin and a second pin for receiving a differential input signal according to a first voltage standard;   a third pin, acting as a center tap pin, coupled to the first pin by a first termination resistance and coupled to the second pin by a second termination resistance, the first termination resistance and the second termination resistance being internal to the integrated circuit package, the third pin for being coupled to a reference node, wherein said reference node is chosen based on said first voltage standard,   wherein the third pin is directly connected to a junction between the first termination resistance and the second termination resistance such that there is no additional resistance between the third pin and the junction;   a differential amplifier internal to the integrated circuit package for receiving the input signal;   at least a fourth pin for outputting an output signal controlled by the input signal; and   a fifth pin of the integrated circuit package, the fifth pin receiving a reference voltage generated internal to the integrated circuit package, the fifth pin for being connected to the third pin as a reference voltage for AC coupled input signals.   
     
     
       29. A structure according to claim 28, wherein said first voltage standard is CML, and said reference node is an open, or not connected, node. 
     
     
       30. A structure according to claim 28, wherein said first voltage standard is CML, said input signal is AC-coupled to said circuit, and said reference node is an AC reference node. 
     
     
       31. A structure according to claim 28, wherein said first voltage standard is PECL, and said reference node has a voltage (VCC-2V). 
     
     
       32. A structure according to claim 28, wherein said first voltage standard is PECL, said input signal is AC-coupled to said circuit, and said reference node is an AC reference node. 
     
     
       33. A structure according to claim 28, wherein said first voltage standard is LVDS, and said reference node is an open, or not connected, node. 
     
     
       34. A structure according to claim 28, wherein said first voltage standard is HSTL and said reference node is a ground node. 
     
     
       35. A structure according to claim 28 wherein the reference voltage generated at the fifth pin is nominally a supply voltage (Vcc) minus 1.4 volts. 
     
     
       36. A structure according to claim 28 wherein the first termination resistance is 50Ω, and the second termination resistance is 50Ω. 
     
     
       37. A structure according to claim 36 where the first termination resistance and the second termination resistance are resistors.