Thin film transistor panel for liquid crystal display

Abstract

A thin film transistor array panel is provided, which includes: an insulating substrate; a first signal wire formed on the insulating substrate; a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; first and second pixel electrodes formed in a pixel area defined by the intersections of the first and the second signal wires and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; and a first thin film transistor connected to the direction control electrode, the first signal wire, and the second signal wire.

What is claimed is: 
     
       1. A thin film transistor array panel comprising:
 an insulating substrate; 
 a first signal wire formed on the insulating substrate; 
 a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; 
 a first pixel electrode and a second pixel electrode formed in a pixel area defined by the intersections of the first signal wire and the second signal wire; 
 a coupling electrode formed in the pixel area and overlapping at least one of the first pixel electrode and the second pixel electrode; and 
 a first thin film transistor connected with the coupling electrode, the first signal wire, and the second signal wire. 
 
     
     
       2. The thin film transistor array panel of  claim 1 , wherein a voltage applied to the first pixel electrode is different from a voltage applied to the second pbcel pixel electrode. 
     
     
       3. The thin film transistor array panel of  claim 1 , wherein the first pixel electrode and the second pixel electrode include a plurality of sub-areas partioned by a plurality of cutouts. 
     
     
       4. The thin film transistor array panel of  claim 3 , wherein a voltage applied to the first pixel electrode is different from a voltage applied to the second pixel electrode. 
     
     
       5. The thin film transistor array panel of  claim 3 , wherein the cutouts of the second pixel electrode comprise a transverse cutout bisecting the second pixel electrode into upper and lower halves and a plurality of first oblique cutouts inversely symmetrical with respect to the transverse cutout, and
 wherein the cutouts of the first pixel electrode comprise a plurality of second oblique cutouts inversely symmetrical with the transverse cutout. 
 
     
     
       6. The thin film transistor array panel of  claim 3 , wherein the first pixel electrode and the second pixel electrode are inversely symmetrical with the transverse cutout. 
     
     
       7. The thin film transistor array panel of  claim 6 , further comprising:
 a third signal wire intersecting the second signal wire in an insulating manner and including an electrode disposed between the first pixel electrode and the second pixel electrode. 
 
     
     
       8. The thin film transistor array panel of  claim 1 , further comprising:
 a second thin film transistor connected with the first pixel electrode, the first signal wire, and the second signal wire. 
 
     
     
       9. The thin film transistor array panel of  claim 8 , further comprising:
 a third thin film transistor connected with the first pixel electrode, the first signal wire, and the second signal wire. 
 
     
     
       10. The thin film transistor array panel of  claim 1 , further comprising a third signal wire intersecting the second signal wire in an insulating manner. 
     
     
       11. A liquid crystal display, comprising;
 a first substrate;   a plurality of first signal lines on the substrate;   a plurality of pixels disposed in a matrix on the first substrate, one of the plurality of pixels comprising a first pixel electrode electrically connected to a first transistor and a second pixel electrode separated from the first pixel electrode, wherein the pixel is disposed between two consecutive first signal lines of the plurality of first signal lines;   a second substrate facing the first substrate and having a common electrode; and   a liquid crystal layer interposed between the first substrate and the second substrate and comprising a plurality of liquid crystal molecules,   wherein the liquid crystal layer on one of the first pixel electrode and the second pixel electrode in the pixel is divided into at least four domains,   wherein each domain is defined by a single orientation direction of the liquid crystal molecules different from all of the other domains when a voltage is applied to one of the first pixel electrode and the second pixel electrode,   wherein an electric field generated between the first electrode and the common electrode is different from an electric field generated between the second electrode and the common electrode, and   wherein orientation directions of the liquid crystal molecules of the at least four domains are oblique with respect to one of the plurality of first signal lines.   
     
     
       12. The liquid crystal display of claim 11, wherein the liquid crystal molecules of an individual domain of the at least four domains are vertically aligned with the first substrate in the absence of an applied electric field. 
     
     
       13. The liquid crystal display of claim 12, wherein the at least four domains of the liquid crystal layer are defined by at least one domain-partitioning member. 
     
     
       14. The liquid crystal display of claim 13, wherein the at least one domain-partitioning member is disposed on the first substrate. 
     
     
       15. The liquid crystal display of claim 14, wherein the at least one domain-partitioning member includes a plurality of slits within the first pixel electrode. 
     
     
       16. The liquid crystal display of claim 11, further comprising a coupling electrode which applies an electric field to one of the first pixel electrode and the second pixel electrode,
 wherein the coupling electrode is connected to one of the first pixel electrode and the second pixel electrode.   
     
     
       17. The liquid crystal display of claim 16, wherein the coupling electrode contacts the first pixel electrode via a contact hole through an insulating layer. 
     
     
       18. The liquid crystal display of claim 17, wherein the coupling electrode is overlapped with the second pixel electrode and the insulating layer is disposed therebetween. 
     
     
       19. The liquid crystal display of claim 18, further comprising a plurality of storage electrode lines each of which are disposed between two adjacent first signal lines of the plurality of first signal lines. 
     
     
       20. The liquid crystal display of claim 19, wherein a storage electrode line of the plurality of storage electrode lines is capacitively coupled with the first pixel electrode. 
     
     
       21. The liquid crystal display of claim 20, wherein the storage electrode line of the plurality of storage electrode lines is capacitively coupled with the second pixel electrode. 
     
     
       22. The liquid crystal display of claim 21, wherein the storage electrode line of the plurality of storage electrode lines is overlapped with at least a portion of the first pixel electrode and the second pixel electrode. 
     
     
       23. The liquid crystal display of claim 22, wherein the coupling electrode is overlapped with the storage electrode line of the plurality of storage electrode signal lines. 
     
     
       24. The liquid crystal display of claim 21, wherein a surface area of the first pixel electrode is different from a surface area of the second pixel electrode. 
     
     
       25. The liquid crystal display of claim 24, wherein a shape of a boundary of the first pixel electrode is different from a shape of a boundary of the second pixel electrode. 
     
     
       26. The liquid crystal display of claim 25, wherein the boundary of the first pixel electrode and the boundary of the second pixel electrode are both polygonal. 
     
     
       27. The liquid crystal display of claim 25, wherein the surface area of the first pixel cleclrode is 30% to 70% of a surface area of an individual pixel. 
     
     
       28. The liquid crystal display of claim 11, wherein a shape of a boundary of the first pixel electrode is different from a shape of a boundary of the second pixel electrode. 
     
     
       29. The liquid crystal display of claim 28, wherein the boundary of the first pixel electrode and the boundary of the second pixel electrode are both polygonal. 
     
     
       30. The liquid crystal display of claim 11, wherein the liquid crystal layer vertically aligned with each of the first pixel electrode and the second pixel electrode in a single pixel of the plurality of pixels is divided into four domains. 
     
     
       31. The liquid crystal display of claim 11, wherein the first pixel electrode and the second pixel electrode of each pixel of the plurality of pixels are disposed in a same layer of the liquid crystal display. 
     
     
       32. The thin film transistor array panel of claim 1, wherein the pixel area is defined by the intersections of the first and the second signal wires.