Long instruction word controlling plural independent processor operations

Abstract

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

We claim: 
     
       1. A data processing apparatus comprising:
 a first input bus register of N bits; 
 a second input bus register of N bits; 
 a multiplier having a first input of L bits connected to receive a first set of L bits of said first input bus register, L being less than N, a second input of L bits connected to receive a second set of L bits of said second input bus register, and a product output of 2L bits producing a product of data that was supplied to said first and second inputs; 
 a left shifter having an input connected to receive the product output of said multiplier, a shift amount input and having an output connected to said output bus, said left shifter left shifting said input by said shift amount, discarding said shift amount of at least one most significant bits bit of said input product output, the left shifter producing a shifted result at said output; and 
 an output bus register of N bits coupled connected to receive said output of said left shifter, said output bus including register storing a first portion corresponding to a most significant set of L bits of said product output of 2L bits shifted result and a second portion of M bits, where said second portion of M bits does not include a least significant set of is not connected to receive the remaining L bits of said product shifted result, and where N=L+M and M≧L. 
 
     
     
       2. The data processing apparatus of  claim 1 , wherein:
 said left shifter further includes a shift amount input controlling a shift amount of said left shifter; and 
 the data processing apparatus further comprising: 
 a data register file including
 a plurality of data registers, each data register storing a plurality of N bits of data, said plurality of data registers including said first register, said second register, said output register and a special function data register including a shift amount field, 
 a first output bus connected to said first input bus register for recalling from a said first specified data register said N bits stored therein, 
 a second output bus connected to said shift amount input of said left shifter for recalling from said special function data register said N bits a shift amount stored therein in said shift amount field, 
 a third output bus connected to said second input bus register for recalling from a third specified data said second register said N bits stored therein, and 
 a first input bus connected to said output of N bits said left shifter for storing in a fourth specified one of said data registers said combination of said first, second and third input signals said output register said first portion of bits and said second portion of bits. 
 
 
     
     
       3. The data processing apparatus of  claim 1 , further comprising:
 a rounder having an input connected to receive the output of said left shifter, and an output connected to said output bus register, said rounder forming a rounded product. 
 
     
     
       4. The data processing apparatus of  claim 3 , further comprising:
 a data register file including a plurality of data registers, each data register storing a plurality of N bits of data, said plurality of data registers including said first register, said second register, said output register, and a special function data register having a rounding bit; and 
 wherein said rounder is selectively enabled if said rounding bit has a first state and not enabled if said rounding bit has a second state different from said first state. 
 
     
     
       5. The data processing apparatus of  claim 3 , wherein:
 said rounder is selectively enabled if a predetermined rounding bit in an instruction has a first state and not enabled if said predetermined rounding bit has a second state different from said first state. 
 
     
     
       6. The data processing apparatus of  claim 1 , wherein:
 said second portion of M bits of said output bus register are derived from at least some bits of at least one of said first N bit input bus register other than said first set of L bits and said second N bit input bus register other than said second set of L bits. 
 
     
     
       7. The data processing apparatus of  claim 1 , wherein:
 said second portion of M bits of said output bus register consists of bits of said first input bus register other than said first set of L bits. 
 
     
     
       8. The data processing apparatus of  claim 1 , further comprising:
 a data register file including
 a plurality of data registers for storing data including said first register, said second register and said output register, 
 a first source output bus connected to said first input bus register for recalling data stored in a said first data register of said plurality of data registers, said first register specified by a multiply instruction, 
 a second source output bus connected to said second input bus register for recalling data stored in a said second data register of said plurality of data registers, said second register specified by a multiply instruction, and 
 a first destination input bus connected to said output bus register for storing said first portion and said second portion of bits in a third data said output register of said plurality of data registers data on said output bus, said output register specified by a multiply instruction. 
 
 
     
     
       9. The data processing apparatus of  claim 1 , wherein:
 said number of bits M is greater than said number of bits L. 
 
     
     
       10. The data processing apparatus of  claim 1 , wherein:
 said number of bits L equals 16 bits. 
 
     
     
       11. The data processing apparatus of  claim 1 , wherein;
 said number of bits L equals 8 bits. 
 
     
     
       12. The data processing apparatus of  claim 1 , wherein:
 said left shifter is further operable to zero fill said a shift amount of least significant bits of said input. 
 
     
     
       13. A data processing apparatus comprising:
 a first input bus register of N bits; 
 a second input bus register of N bits; 
 a multiplier having a first input of L bits connected to receive a first set of L bits of said first input bus register, L being less than N, a second input of L bits connected to receive a second set of L bits of said second input bus register, and a product output of 2L bits producing a product of data that was supplied to said first and second inputs; 
 a left shifter having an input connected to receive the product output of said multiplier, a shift amount input and an output connected to said output bus, said left shifter left shifting said input by said shift amount, discarding said shift amount of at least one most significant bits bit of said input product output, the left shifter producing a shifted result at said output, the left shifter zero filling the least significant bits of the shifted result by the same number of bits that were discarded; and 
 an output bus register of N bits coupled connected to receive said output of said left shifter, said output bus including register storing a first portion of L bits corresponding to a most significant set of L bits of said product output of 2L bits shifted result and a second portion of M bits, said second portion of M bits not including the least significant bits of said product output, where N=L+M and M≧L. 
 
     
     
       14. The data processing apparatus of  claim 13 , wherein:
 said left shifter further includes a shift amount input controlling a shift amount of said left shifter; and 
 the data processing apparatus further comprising: 
 a data register file including
 a plurality of data registers, including said first register, said second register and said output register specified by a single instruction, each data register storing a plurality of N bits of data, said plurality of data registers further including a special function data register including a shift amount field for storing a shift amount, 
 a first output bus connected to said first input bus register for recalling from a said first specified data register specified by said single instruction said N bits stored therein, 
 a second output bus connected to said shift amount input of said left shifter for recalling from said special function data register said N bits a shift amount stored therein, 
 a third output bus connected to said second input bus register for recalling from a third specified data said second register specified by said single instruction said N bits stored therein, and 
 a first input bus connected to said output of N bits said left shifter for storing in a fourth specified one of said data registers said combination of said first, second and third input signals said output register specified by said single instruction said first portion and said second portion of bits. 
 
 
     
     
       15. The data processing apparatus of  claim 13 , further comprising:
 a rounder having an input connected to receive the output of said left shifter, and an output connected to said output bus register, said rounder forming a rounded product. 
 
     
     
       16. The data processing apparatus of  claim 15 , further comprising:
 a data register file including a plurality of data registers, each data register storing a plurality of N bits of data, said plurality of data registers including said first register, said second register, said output register and a special function data register having a rounding bit; and 
 wherein said rounder is selectively enabled if said rounding bit has a first state and not enabled if said rounding bit has a second state different from said first state. 
 
     
     
       17. The data processing apparatus of  claim 15 , wherein:
 said rounder is selectively enabled if a predetermined rounding bit in an instruction has a first state and not enabled if said predetermined rounding bit has a second state different from said first state. 
 
     
     
       18. The data processing apparatus of  claim 13 , further comprising:
 a data register file including
 a plurality of data registers for storing data including said first register, said second register and said output register, said first register, said second register and said output register specified by a single instruction, 
 a first source output bus connected to said first input bus register for recalling data stored in a the first set of L bits from said first data register of said plurality of data registers specified by said single instruction, 
 a second source output bus connected to said second input bus register for recalling data stored in a the second set of L bits from said second data register of said plurality of data registers specified by said single instruction, and 
 a first destination input bus connected to said output bus register for storing said first portion of L bits and said second portion of M bits in a third data said output register of said plurality of data registers data on said output bus specified by said single instruction. 
 
 
     
     
       19. The data processing apparatus of  claim 13 , wherein:
 said number of bits L equals 16 bits. 
 
     
     
       20. The data processing apparatus of  claim 13 , wherein;
 said number of bits L equals 8 bits. 
 
     
     
       21. The data processing apparatus of  claim 13 , wherein:
 said left shifter is further operable to zero fill said a shift amount of least significant bits of said input. 
 
     
     
       22. A data processing apparatus comprising:
 a first input bus register of N bits; 
 a second input bus register of N bits; 
 a multiplier having a first input of L bits connected receive to a first set of L bits of from said first input bus register, L being less than N, a second input of L bits connected to receive a second set of L bits of from said second input bus register, and a product output of 2L bits producing a product of data that was supplied to said first and second inputs; 
 a rounder having a first an input connected to receive L most significant L bits of the product output of said multiplier a second input connected to a L+1 most significant bit of said product output and an output connected to said output bus forming a rounded product, said rounder rounding the L most significant bits of said product dependent on the L+1 most significant bit of said product, said rounder producing a rounded result of L bits; and 
 an output bus register of N bits coupled connected to receive said output of said rounder, said output bus including register including a first portion corresponding to a most significant set of L bits of said output of said rounder and a second portion of M bits, where said second portion of M bits does not include a least significant set of L bits of said product, and where N=L+M and M≧L. 
 
     
     
       23. The data processing apparatus of  claim 22 , further comprising:
 a data register file including a plurality of data registers including said first register, said second register and said output register, each data register storing a plurality of N bits of data, said plurality of data registers including a special function data register having a rounding bit; and 
 wherein said rounder is selectively enabled if said rounding bit has a first state and not enabled if said rounding bit has a second state different from said first state. 
 
     
     
       24. The data processing apparatus of  claim 22 , wherein:
 said rounder is selectively enabled if a predetermined rounding bit in an instruction has a first state and not enabled if said predetermined rounding bit has a second state different from said first state. 
 
     
     
       25. The data processing apparatus of  claim 22 , wherein:
 said second portion of M bits of said output bus register are derived from at least some bits of at least one of said first N bit input bus register other than said first set of L bits and said second N bit input bus register other than said second set of L bits. 
 
     
     
       26. The data processing apparatus of  claim 22 , wherein:
 said second portion of M bits of said output bus register consists of bits of said first input bus register other than said first set of L bits. 
 
     
     
       27. The data processing apparatus of  claim 22 , further comprising:
 a data register file including
 a plurality of data registers for storing data including said first register, said second register and said output register, said first register, said second register and said output register specified by a single instruction, 
 a first source output bus connected to said first input bus register for recalling data stored in a said first data register of said plurality of data registers, 
 a second source output bus connected to said second input bus register for recalling data stored in a said second data register of said plurality of data registers, and 
 a first destination input bus connected to said output bus register for storing said first portion and said second portion of bits in a third data said output register of said plurality of data registers data on said output bus. 
 
 
     
     
       28. The data processing apparatus of  claim 22 , wherein:
 said number of bits M is greater than said number of bits L. 
 
     
     
       29. The data processing apparatus of  claim 22 , wherein:
 said number of bits L equals 16 bits. 
 
     
     
       30. The data processing apparatus of  claim 22 , wherein;
 said number of bits L equals 8 bits. 
 
     
     
       31. The data processing apparatus of claim 26, further comprising:
 circuitry connected to receive the output of the multiplier and said rounder, said circuitry zero filling at least one least significant bit of the product output of 2L bits.   
     
     
       32. The data processing apparatus of claim 26, wherein;
 said rounder increments the most significant L bits of said product if the L+1 most significant bit of said product is a “1”.   
     
     
       33. The data processing apparatus of claim 22, wherein:
 said input of said rounder including a first input connected to receive L most significant bits of said product output of said multiplier and a second input connected to receive a L+1 most significant bit of said product output, said rounder rounding the L most significant bits of said product dependent on the L+1 most significant bit of said product.   
     
     
       34. A data processing apparatus comprising:
 a first register of N bits;   a second register of N bits;   a multiplier having a first input of L bits connected to receive a first set of L bits of said first register, L being less than N, a second input of L bits connected to receive a second set of L bits of said second register, and a product output of 2L bits, the multiplier producing a product of data that was supplied to said first and second inputs;   circuitry having an input connected to receive the product output of said multiplier and having an output, said circuitry producing an L bit rounded result, said rounded result not including at least one most significant bit of said product output; and   an output register of N bits connected to receive said output of said circuitry, said output register including a first portion corresponding to said L bit rounded result and a second portion of M bits, where said second portion of M bits does not include a least significant set of L bits of said product, and where N=L+M and M≧L.   
     
     
       35. The data processing apparatus of claim 34, wherein:
 said circuitry includes a left shifter circuit discarding the at least one most significant bit of the product output and producing a shifted output.   
     
     
       36. The data processing apparatus of claim 35, wherein:
 said circuitry further includes a rounder circuit connected to receive the L+1 most significant bits of said shifted output, said rounder circuit producing said L bit rounded result dependent upon the value of a L+1 most significant bit of said shifted output.   
     
     
       37. The data processing apparatus of claim 35, wherein:
 said left shifter is further operable to zero fill in said shifted output and at least one least significant bit of said product output equal in number to said at least one most significant bit of said product output.   
     
     
       38. The data processing apparatus of claim 34, wherein:
 said circuitry includes a rounder circuit, the rounder circuit receiving L+1 consecutive bits of said product output and producing said L bit rounded result dependent upon the value of a least significant bit of the L+1 consecutive bits.   
     
     
       39. The data processing apparatus of claim 34, wherein:
 said rounded result does not include up to 3 most significant bits of said product output.   
     
     
       40. The data processing apparatus of claim 22, wherein:
 said rounder rounds the L most significant bits dependent upon the L+1 most significant bit of said product.   
     
     
       41. The data processing apparatus of claim 34, further comprising:
 a data register file including
 a plurality of data registers for storing data including said first register, said second register and said output register, 
 a first source output bus connected to said first data register for recalling data stored in said first register of said plurality of data registers, said first register specified by a multiply instruction, 
 a second source output bus connected to said second register for recalling data stored in said second register of said plurality of data registers, said second register specified by said multiply instruction, and 
 a first destination input bus connected to said output register for storing said first portion and said second portion of bits in said output register of said plurality of data registers, said output register specified by said multiply instruction.