Semiconductor memory

Abstract

A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I 1 ) consists of a NMOS transistor (N 1 ) and a PMOS transistor (P 1 ), and an inverter (I 2 ) consists of a NMOS transistor (N 2 ) and a PMOS transistor (P 2 ). The inverters (I 1, I 2 ) are subjected to cross section. The NMOS transistor (N 1 ) is formed within a P well region (PW 0 ), and the NMOS transistor (N 2 ) is formed within a P well region (PW 1 ). The P well regions (PW 0, PW 1 ) are oppositely disposed with an N well region (NW) interposed therebetween.

What is claimed is: 
     
       1. A semiconductor memory comprising:
 a memory cell having first and second storage terminals storing information of logic levels complementary to each other;   a power supply wiring supplying a predetermined power supply voltage to said memory cell;   first and second pairs of bit lines each electrically connected to said first and second storage terminals of said memory cell, when selected; and   first and second word lines connected to said memory cell, said first pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said first word line, and said second pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said second word line, wherein
 said first and second pairs of bit lines and said power supply wiring are provided in parallel to each other, with said power supply wiring interposed between said first and second pairs of bit lines. 
   
     
     
       2. The semiconductor memory according to  claim 1 , further comprising:
 first and second ground wirings each supplying a predetermined ground potential to said memory cell, wherein
 said first pair of bit lines and said first ground wiring are provided in parallel to each other, with said first ground wiring interposed between said first pair of bit lines, and 
 said second pair of bit lines and said second ground wiring are provided in parallel to each other, with said second ground wiring interposed between said second pair of bit lines. 
   
     
     
       3. The semiconductor memory according to  claim 1 , wherein
 said memory cell is formed on first and second P wells and an N well interposed between said first and second P wells in a first direction, and said power supply wiring extending along a second direction vertical to said first direction is formed on said N well.   
     
     
       4. A semiconductor device having a two-port type static random access memory, one memory cell of which includes first to eighth transistor, comprising:
 first and second well regions of a first conductivity type,   a third well region of a second conductivity type disposed between the first and second well regions in a plane view;   a first pair of impurity regions of the first conductivity type provided in the third well region, functioning as two electrodes of the first transistor;   a second pair of impurity regions of the first conductivity type provided in the third well region, functioning as two electrodes of the second transistor;   a third pair of impurity regions of the second conductivity type provided in the first well region, functioning as two electrodes of the third transistor;   a fourth pair of impurity regions of the second conductivity type provided in the first well region, functioning as two electrodes of the fourth transistor;   a fifth pair of impurity regions of the second conductivity type provided in the first well region, functioning as two electrodes of the fifth transistor;   a sixth pair of impurity regions of the second conductivity type provided in the second well region, functioning as two electrodes of the sixth transistor;   a seventh pair of impurity regions of the second conductivity type provided in the second well region, functioning as two electrodes of the seventh transistor;   an eighth pair of impurity regions of the second conductivity type provided in the second well region, functioning as two electrodes of the eighth transistor;   a first conductive layer provided over the first and third well regions, functioning as a gate electrode common to the first and third transistors;   a second conductive layer provided over the second and third well regions, functioning as a gate electrode common to the second and sixth transistors;   a third conductive layer provided over the first well region, functioning as a gate electrode common to the fourth and fifth transistors;   a fourth conductive layer provided over the second well region, functioning as a gate electrode common to the seventh and eighth transistors;   a fifth conductive layer electrically connected to the second conductive layer, one of the first pair of impurity regions, one of the third pair of impurity regions, one of the fourth pair of impurity regions and one of the eighth pair of impurity regions, and functioning as one storage terminal of the one memory cell;   a sixth conductive layer electrically connected to the first conductive layer, one of the second pair of impurity regions, one of the sixth pair of impurity regions, one of the seventh pair of impurity regions and one of the fifth pair of impurity regions, and functioning as another storage terminal of the one memory cell;   a first word line electrically connected to the third conductive layer;   a second word line electrically connected to the fourth conductive layer;   a first bit line electrically connected to the other of the fourth pair of impurity regions;   a second bit line electrically connected to the other of the fifth pair of impurity regions;   a third bit line electrically connected to the other of the seventh pair of impurity regions; and   a fourth bit line electrically connected to the other of the eighth pair of impurity regions.    
     
     
       5. The semiconductor device according to claim 4, wherein
 the ones of the third and fourth pairs of impurity regions are a common impurity region, and the ones of the sixth and seventh pairs of impurity regions are a common impurity region.    
     
     
       6. The semiconductor device according to claim 4, wherein
 the one of the first pair of impurity regions is electrically connected to the fifth conductive layer via a first contact hole disposed between overlapped portions of the fifth conductive layer and the one of the first pair of impurity regions in the plane view,   the one of the third pair of impurity regions is electrically connected to the fifth conductive layer via a second contact hole disposed between overlapped portions of the fifth conductive layer and the one of the third pair of impurity regions in the plane view,   the one of the eighth pair of impurity regions is electrically connected to the fifth conductive layer via a third contact hole disposed between overlapped   portions of the fifth conductive layer and the one of the eighth impurity regions in the plane view,   the one of the second pair of impurity regions is electrically connected to the sixth conductive layer via a fourth contact hole disposed between overlapped portions of the sixth conductive layer and the one of the second pair of impurity regions in the plane view,   the one of the sixth pair of impurity regions is electrically connected to the sixth conductive layer via a fifth contact hole disposed between overlapped portions of the sixth conductive layer and the one of the sixth pair of impurity regions in the plane view, and   the one of the fifth pair of impurity regions is electrically connected to the sixth conductive layer via a sixth contact hole disposed between overlapped portions of the sixth conductive layer and the one of the fifth pair of impurity regions in the plane view.    
     
     
       7. The semiconductor device according to claim 6, wherein
 the second conductive layer is electrically connected to the fifth conductive layer via a seventh contact hole disposed between overlapped portions of the second and fifth conductive layers in the plane view, and   the first conductive layer is electrically connected to the sixth conductive layer via an eighth contact hole disposed between overlapped portions of the first and sixth conductive layers in the plane view.    
     
     
       8. The semiconductor device according to claim 4, wherein
 the one of the first pair of impurity regions and the second conductive layer are electrically connected to the fifth conductive layer via a first shared contact disposed between overlapped portions of the fifth conductive layer and the one of the first pair of impurity regions in the plane view,   the one of the third pair of impurity regions is an impurity region common to the one of the fourth pair of impurity regions, and is electrically connected to the fifth conductive layer via a first contact hole disposed between overlapped portions of the fifth conductive layer and the one of the third pair of impurity regions in the plane view,   the one of the eighth pair of impurity regions is electrically connected to the second conductive layer via a second shared contact,   the one of the second pair of impurity regions and the first conductive layer are electrically connected to the sixth conductive layer via a third shared contact disposed between overlapped portions of the sixth conductive layer and the one of the second pair of impurity regions in the plane view,   the one of the sixth pair of impurity regions is an impurity region common to the one of the seventh pair of impurity regions, and is electrically connected to the sixth conductive layer via a second contact hole disposed between overlapped portions of the sixth conductive layer and the one of the sixth impurity regions in the plane view, and   the one of the fifth pair of impurity regions is electrically connected to the first conductive layer via a fourth shared contact.