Nonvolatile semiconductor memory including multi-threshold voltage memory cells including voltage ranges indicating either an erase state or a two or more program state

Abstract

In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multi-valued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

What we claim is: 
     
       1. A nonvolatile memory apparatus comprising:
 a central processing unit; and   a nonvolatile memory,   wherein said central processing unit is capable of outputting a plurality of commands, an address, a write enable signal, a clock signal and data,   wherein said commands includes a program command, wherein said nonvolatile memory comprises a plurality of word lines and a plurality of memory cells each of which has a threshold voltage within one of a plurality of threshold voltage distributions,   wherein one of said threshold voltage distributions is assigned to an erase state and others of said threshold voltage distributions are assigned to program states, respectively,   wherein said nonvolatile memory receives said commands and said address during an enable state of said write enable signal and receives said data in response to said clock signal during a disable state of said write enable signal, and   wherein in an operation of said program command, said nonvolatile memory controls selection of one word line according to said address received from said central processing unit and brings said threshold voltage of memory cells coupled to said selected word line from the erase state threshold voltage distribution to one of program state threshold voltage distributions corresponding to data to be stored in respective ones of said memory cells.   
     
     
       2. A nonvolatile memory apparatus according to  claim 1 , wherein said central processing unit is capable of outputting said commands during an enable state of a command enable signal and is capable of outputting said address during a disable state of said command enable signal. 
     
     
       3. A nonvolatile memory apparatus according to  claim 2 ,
 wherein each of said memory cells is capable of storing a two bit data.   
     
     
       4. A nonvolatile memory apparatus according to  claim 3 ,
 wherein said nonvolatile memory brings said threshold voltage of memory cells to be within that one of the program state threshold voltage distributions having the lowest voltage, firstly.   
     
     
       5. A nonvolatile memory apparatus according to  claim 4 ,
 wherein said erase state is assigned to that one of said threshold voltage distributions having the highest voltage.   
     
     
       6. A nonvolatile memory apparatus according to  claim 2 ,
 wherein said nonvolatile memory brings said threshold voltage of memory cells to be within that one of the program state threshold voltage distributions having the lowest voltage, firstly.   
     
     
       7. A nonvolatile memory apparatus according to  claim 6 ,
 wherein said erase state is assigned to that one of said threshold voltage distributions having the highest voltage.   
     
     
       8. A nonvolatile memory apparatus comprising:
 a central processing unit; and   a nonvolatile memory,   wherein said central processing unit is capable of outputting a plurality of commands, an address, a write enable signal, a clock signal and data,   wherein said commands includes a program command,   wherein said nonvolatile memory comprises a plurality of I/O terminals, a plurality of word lines and a plurality of memory cells each of which has a threshold voltage within a plurality of threshold voltage distributions,   wherein one of said threshold voltage distributions is assigned to an erase state and others of said threshold voltage distributions are assigned to program states, respectively,   wherein said nonvolatile memory receives said commands, said address and said data via said I/O terminals, receives said commands and said address in response to a first state of said write enable signal and receives said data in response to said clock signal in a second state of said write enable signal,   wherein in an operation of said program command, said nonvolatile memory controls selection of one word line according to said address received from said central processing unit and brings said threshold voltage of memory cells coupled to said selected word line from the erase state threshold voltage distribution to one of program state threshold voltage distributions corresponding to data to be stored in respective ones of said memory cells.   
     
     
       9. A nonvolatile memory apparatus according to  claim 8 ,
 wherein said central processing unit is capable of outputting said commands during an enable state of a command enable signal and is capable of outputting said address during a disable state of said command enable signal.   
     
     
       10. A nonvolatile memory apparatus according to  claim 9 ,
 wherein each of said memory cells is capable of storing a two bit data.   
     
     
       11. A nonvolatile memory apparatus according to  claim 10 ,
 wherein said nonvolatile memory brings said threshold voltage of memory cells to be within that one of the program state threshold voltage distributions having the lowest voltage, firstly.   
     
     
       12. A nonvolatile memory apparatus according to  claim 11 ,
 wherein said erase state is assigned to that one of said threshold voltage distributions having the highest voltage.   
     
     
       13. A nonvolatile memory apparatus according to  claim 9 ,
 wherein said nonvolatile memory brings said threshold voltage of memory cells to be within that one of the program state threshold voltage distributions having the lowest voltage, firstly.   
     
     
       14. A nonvolatile memory apparatus according to  claim 13 ,
 wherein said erase state is assigned to that one of said threshold voltage distributions having the highest voltage.   
     
     
       15. A nonvolatile memory apparatus according to  claim 1 ,
 wherein said central processing unit is provided on a semiconductor substrate different from a semiconductor substrate on which said nonvolatile memory is provided.   
     
     
       16. A nonvolatile memory apparatus according to  claim 1 ,
 wherein said central processing unit is included in a large-scale integration circuit (LSI), and   wherein said LSI is coupled with terminals of said non-volatile memory.   
     
     
       17. A nonvolatile memory apparatus according to  claim 8 ,
 wherein said central processing unit is provided on a semiconductor substrate different from a semiconductor substrate on which said nonvolatile memory is provided.   
     
     
       18. A nonvolatile memory apparatus according to  claim 17 ,
 wherein said central processing unit is a component in a large-scale integration circuit (LSI), said LSI includes connections with the I/O terminals of said nonvolatile memory.   
     
     
       19. A nonvolatile memory apparatus according to  claim 8 ,
 wherein said central processing unit is included in a large-scale integration circuit (LSI), and   wherein said LSI is coupled with terminals of said non-volatile memory.   
     
     
       20. A nonvolatile memory apparatus according to  claim 1 ,
 wherein said program command and said address commence in synchronism with a same pulse edge of successive pulses of said write enable signal, respectively.   
     
     
       21. A nonvolatile memory apparatus according to  claim 2 ,
 wherein the enable state and the disable state of said command enable signal commence simultaneously with the program command and the data address, respectively.   
     
     
       22. A nonvolatile memory apparatus according to  claim 8 ,
 wherein said program command and said address commence in synchronism with a same pulse edge of successive pulses of said write enable signal, respectively.   
     
     
       23. A nonvolatile memory apparatus according to  claim 9 ,
 wherein the enable state and disable state of said command enable signal commence simultaneously with the program command and the data address, respectively.   
     
     
       24. A nonvolatile semiconductor memory comprising:
 a plurality of nonvolatile memory cells, each of which has a control gate and a floating gate, and is capable of storing data corresponding to a difference of a threshold voltage thereof,   a plurality of word lines, each of which couples with corresponding nonvolatile memory cells;   a plurality of data lines, each of which couples with corresponding nonvolatile memory cells; and   a plurality of latch circuits, each of which couples with a corresponding data line,   wherein each of the nonvolatile memory cells is adapted to set the threshold voltage thereof into one of a voltage range indicating an erase state and voltage ranges indicating two or more program states,   wherein in a program operation, the threshold voltage of a nonvolatile memory cell is shifted to a first voltage range indicating a first program state, the voltage range of which is the closest to the voltage range indicating the erase state, and, afterwards, the threshold voltage of the nonvolatile memory cell to be set to a second voltage range is shifted to the second voltage range indicating a second program state, the voltage range of which is farther than that of the first voltage range from the voltage range indicating the erase state,   wherein in a verify operation in response to the program operation, with regard to the nonvolatile memory cell to be set to have the threshold voltage thereof in the first voltage range, it is verified whether the threshold voltage thereof is over a near limit of the first voltage range from the voltage range indicating the erase state and it is verified whether the threshold voltage thereof does not go over a far limit of the first voltage range from the voltage range indicating the erase state, and with regard to the nonvolatile memory cell to be set to have the threshold voltage thereof in the second voltage range, it is verified whether the threshold voltage thereof is over a near limit of the second voltage range from the voltage range indicating the erase state and it is verified whether the threshold voltage thereof does not go over a far limit of the second voltage range from the voltage range indicating the erase state,   wherein there is a third voltage range indicating a third program state in the voltage ranges indicating the program states,   wherein the third voltage range indicating the third program state is farther than the second voltage range indicating the second program state from the voltage range indicating the erase state,   wherein in the verify operation, with regard to the nonvolatile memory cell to be set to have the threshold voltage thereof in the third voltage range, it is verified whether the threshold voltage thereof is over a near limit of the third voltage range from the voltage range indicating the erase state and it is not verified whether the threshold voltage thereof does not go over the far limit of the third voltage range from the voltage range indicating the erase state,   wherein a second read voltage for discriminating between the second voltage range and the third voltage range is between the far limit of the second voltage range and the near limit of the third voltage range,   wherein in the verify operation, the threshold voltage of each of the nonvolatile memory cells coupled to one word line is checked by supplying a verify voltage to the one word line, and   wherein in the program operation, the threshold voltage of the nonvolatile memory cell to be set to the third voltage range is shifted to the third voltage range before the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is shifted to a second voltage range.   
     
     
       25. A nonvolatile semiconductor memory according to claim 24,
 wherein the program operation is finished when the threshold voltage of the nonvolatile memory cell to be set to the first voltage range is over the near limit of the first voltage range or the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is over the near limit of the second voltage range, and then   wherein the verify operation is performed in order that the threshold voltage of the nonvolatile memory cell to be set to the first voltage range is over or not the far limit of the first voltage range or the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is over or not the far limit of the second voltage range.   
     
     
       26. A nonvolatile semiconductor memory according to claim 25,
 wherein the memory is adapted to issue a signal to outside for notifying an occurrence that the threshold voltage of the nonvolatile memory cell to be set to the first voltage range is over the far limit of the first voltage range or the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is over the far limit of the second voltage range.   
     
     
       27. A nonvolatile memory apparatus comprising:
 a semiconductor circuit; and   the nonvolatile semiconductor memory comprising a plurality of nonvolatile memory cells, each of which has a control gate and a floating gate, and is capable of storing data corresponding to a difference of a threshold voltage thereof,   a plurality of word lines, each of which couples with corresponding nonvolatile memory cells;   a plurality of data lines, each of which couples with corresponding nonvolatile memory cells; and   a plurality of latch circuits, each of which couples with a corresponding data line,   wherein each of the nonvolatile memory cells is adapted to set the threshold voltage thereof into one of a voltage range indicating an erase state and voltage ranges indicating two or more program states,   wherein in a program operation, the threshold voltage of a nonvolatile memory cell is shifted to a first voltage range indicating a first program state, the voltage range of which is the closest to the voltage range indicating the erase state, and, afterwards, the threshold voltage of the nonvolatile memory cell to be set to a second voltage range is shifted to the second voltage range indicating a second program state, the voltage range of which is farther than that of the first voltage range from the voltage range indicating the erase state,   wherein in a verify operation in response to the program operation, with regard to the nonvolatile memory cell to be set to have the threshold voltage thereof in the first voltage range, it is verified whether the threshold voltage thereof is over a near limit of the first voltage range from the voltage range indicating the erase state and it is verified whether the threshold voltage thereof does not go over a far limit of the first voltage range from the voltage range indicating the erase state, and with regard to the nonvolatile memory cell to be set to have the threshold voltage thereof in the second voltage range, it is verified whether the threshold voltage thereof is over a near limit of the second voltage range from the voltage range indicating the erase state and it is verified whether the threshold voltage thereof does not go over a far limit of the second voltage range from the voltage range indicating the erase state,   wherein there is a third voltage range indicating a third program state in the voltage ranges indicating the program states,   wherein the third voltage range indicating the third program state is farther than the second voltage range indicating the second program state from the voltage range indicating the erase state,   wherein in the verify operation, with regard to the nonvolatile memory cell to be set to have the threshold voltage thereof in the third voltage range, it is verified whether the threshold voltage thereof is over a near limit of the third voltage range from the voltage range indicating the erase state and it is not verified whether the threshold voltage thereof does not go over the far limit of the third voltage range from the voltage range indicating the erase state,   wherein a second read voltage for discriminating between the second voltage range and the third voltage range is between the far limit of the second voltage range and the near limit of the third voltage range,   wherein in the verify operation, the threshold voltage of each of the nonvolatile memory cells coupled to one word line is checked by supplying a verify voltage to the one word line, and   wherein in the program operation, the threshold voltage of the nonvolatile memory cell to be set to the third voltage range is shifted to the third voltage range before the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is shifted to a second voltage range,   wherein the program operation is finished when the threshold voltage of the nonvolatile memory cell to be set to the first voltage range is over the near limit of the first voltage range or the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is over the near limit of the second voltage range, and then   wherein the verify operation is performed in order that the threshold voltage of the nonvolatile memory cell to be set to the first voltage range is over or not the far limit of the first voltage range or the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is over or not the far limit of the second voltage range,   wherein the memory is adapted to issue a signal to outside for notifying an occurrence that the threshold voltage of the nonvolatile memory cell to be set to the first voltage range is over the far limit of the first voltage range or the threshold voltage of the nonvolatile memory cell to be set to the second voltage range is over the far limit of the second voltage range, and   wherein the semiconductor circuit is adapted to issue a predetermined control signal, an address signal, and a data signal to the nonvolatile semiconductor memory.