Charge comparator with low input offset

Abstract

A Direct Current (DC) charge comparator that provides low input offset by feeding complimentary plus and minus charge inputs to a single amplification path via an alternate input path switch. Multiple sample and hold circuits at the output of the amplification path permit comparison of the result when each of the charge inputs travels down each of the paths, to determine a correction.

What is claimed is: 
     
       1. A charge comparator comprising:
 a switch connected to receive a pair of charge inputs as a plus charge input and a minus charge input, with the switch having a first state wherein the plus signal charge is coupled to a first output and the minus signal charge is coupled to a second output, and a second state wherein the plus charge input is coupled to the second output and the minus charge input is coupled to the first output; 
 a pair of charge integrators, connected to the first and second switch outputs, to provide a first integrated output signal and a second integrated output signal; 
 a pair of sample and hold circuits, connected to sample and hold respective ones of the first and second integrated output signals; and 
 a difference amplifier, coupled to the pair of sample and hold circuits, to determine a difference between the outputs of the sample and hold circuits. 
 
     
     
       2. A charge comparator comprising:
 a switch connected to receive a pair of charge inputs as a plus charge input and a minus charge input, with the switch having a first state wherein the plus signal charge is coupled to a first output and the minus signal charge is coupled to a second output, and a second state wherein the plus charge input is coupled to the second output and the minus charge input is coupled to the first output; 
 a pair of charge integrators, connected to the first and second switch outputs, to provide a first integrated output signal and a second integrated output signal; 
 a pair of sample and hold circuits, connected to sample and hold respective ones of the first and second integrated output signals; 
 a difference amplifier, coupled to the pair of sample and hold circuits, to determine a difference between the outputs of the sample and hold circuits; and 
 a signal amplifier, connected to the output of the integrators, to provide an amplified output thereof. 
 
     
     
       3. A charge comparator as in  claim 2  additionally comprising:
 a second pair of sample and hold circuits, connected to cooperate with the first pair of sample and hold circuits, such that in a first mode, the first pair of sample and hold circuits stores respective integrated charge samples from the plus charge input and minus charge input, and such that in a second mode, the second pair of sample and hold circuits stores the plus signal charge and the minus signal charge, respectively. 
 
     
     
       4. A charge comparator as in  claim 3  wherein the difference amplifier is connected to determine the difference between the output of the first pair of sample and hold circuits in a first mode and is connected to determine a difference in the outputs between the second pair of sample and hold circuit outputs in a second mode. 
     
     
       5. A charge comparator as in  claim 2  wherein the charge integrators integrate the respective input charges over multiple clock periods prior to operating the sample and hold circuit. 
     
     
       6. A charge comparator as in  claim 2  additionally wherein the difference amplifier compares a charge integrator result at a first time with a charge integrator result a second time, such that a plus charge input applied with the switch in one state is compared with the plus charge input with the switch compared in another state. 
     
     
       7. A charge comparator as in  claim 2  wherein the amplifier output in a non-inverted switch state is compared to an amplifier output in an inverted switch state, such that when fed to the differential difference amplifier any input offset is amplified in the same way for both the inverted and non-inverted switch conditions, to cancel an input offset. 
     
     
       8. A charge comparator as in  claim 1  additionally comprising:
 a second pair of sample and hold circuits, connected to cooperate with the first pair of sample and hold circuits, such that in a first mode, the first pair of sample and hold circuits stores respective integrated charge samples from the plus charge input and minus charge input, and such that in a second mode, the second pair of sample and hold circuits stores the plus signal charge and the minus signal charge, respectively. 
 
     
     
       9. A charge comparator as in  claim 8  wherein the difference amplifier is connected to determine the difference between the output of the first pair of sample and hold circuits in a first mode and is connected to determine a difference in the outputs between the second pair of sample and hold circuit outputs in a second mode. 
     
     
       10. A charge comparator as in  claim 1  wherein the charge integrators integrate the respective input charges over multiple clock periods prior to operating the sample and hold circuit. 
     
     
       11. A charge comparator as in  claim 1  additionally wherein the difference amplifier compares a charge integrator result at a first time with a charge integrator result a second time, such that a plus charge input applied with the switch in one state is compared with the plus charge input with the switch compared in another state. 
     
     
       12. A charge comparator as in  claim 1  wherein the amplifier output in a non-inverted switch state is compared to an amplifier output in an inverted switch state, such that when fed to the differential difference amplifier any input offset is amplified in the same way for both the inverted and non-inverted switch conditions, to cancel an input offset. 
     
     
       13. An apparatus for converting an input charge to a digital value comprising:
 a first charge pipeline for accepting a first pipeline charge input, and providing a first pipeline charge output;   a second charge pipeline for receiving a second pipeline charge input, and providing a second pipeline charge output;   the first and second charge pipeline inputs representing the input charge as a complimentary pair of input charges;   a first and second reference charge generator, for generating, respectively, a first and second reference charge representing a complimentary pair of reference charges;   a first and second charge domain digital-to-analog converter, coupled to respective ones of the first and second reference charge generators and coupled to respective ones of the first and second charge pipelines, to provide a first and second output charge representative of a complimentary pair of digital values; and   a charge offset sensor coupled to the first and second charge pipeline outputs, the charge offset sensor having   a first sensor state wherein the first pipeline charge output is coupled to a first sensor output and the second pipeline charge output is coupled to a second sensor output,   a second sensor state wherein the first pipeline charge output is coupled to the second sensor output and the second pipeline charge output is coupled to the first sensor output,   a pair of charge integrators, connected to the first and second sensor outputs, to provide a first integrated output signal and a second integrated output signal and   the charge sensor further determining a charge offset introduced by the apparatus by comparing the first integrated output signal provided in the first sensor state to the second integrated output signal provided in the second sensor state, and for also comparing the second integrated output signal provided in the first sensor state to the first integrated output signal provided in the second sensor state.   
     
     
       14. A method for charge comparison comprising:
 receiving a complimentary pair of signal charge inputs as a plus charge input and a minus charge input;   in a first state, coupling the plus charge input to a first output and the minus charge input to a second output,   in a second state, coupling the plus charge input to the second output and the minus charge input to the first output;   integrating the first and second outputs to provide a first integrated output signal and a second integrated output signal;   a first step of sampling and holding respective ones of the first and second integrated output signals in the first state, to provide first and second sample and hold output signals;   a second step of sampling and holding respective ones of the first and second integrated output signals in the second state, to provide third and fourth sample and hold output signals; and   determining a difference between the first and second sample and hold output signals and the third and fourth sample and hold output signals.   
     
     
       15. An apparatus for converting an input charge to a digital value comprising:
 a first charge pipeline for accepting a first pipeline charge input, and providing a first pipeline charge output;   a second charge pipeline for receiving a second pipeline charge input, and providing a second pipeline charge output;   the first and second charge pipeline inputs representing the input charge as a complimentary pair of input charges;   a first and second reference charge generator, for generating, respectively, a first and second reference charge representing a complimentary pair of reference charges;   a first and second charge domain digital-to-analog converter, coupled to respective ones of the first and second reference charge generators and coupled to respective ones of the first and second charge pipelines, to provide a first and second output charge representative of a complimentary pair of digital values; and   a charge offset sensor coupled to the first and second charge pipeline outputs, wherein charge offset sensor further comprises:   a switch connected to receive a pair of charge inputs as a plus charge input and a minus charge input, with the switch having a first state wherein the plus signal charge is coupled to a first output and the minus signal charge is coupled to a second output, and a second state wherein the plus charge input is coupled to the second output and the minus charge input is coupled to the first output; and   a pair of charge integrators, connected to the first and second switch outputs, to provide a first integrated output signal and a second integrated output signal.   
     
     
       16. An apparatus as in claim 15 wherein the charge offset sensor further comprises:
 a pair of sample and hold circuits, connected to sample and hold respective ones of the first and second integrated output signals.   
     
     
       17. An apparatus as in claim 16 wherein the charge offset sensor further comprises:
 a difference amplifier, coupled to the pair of sample and hold circuits, to determine a difference between the outputs of the sample and hold circuits.   
     
     
       18. An apparatus as in claim 17 wherein the charge offset sensor further comprises:
 a signal amplifier, connected to the output of the integrators, to provide an amplified output thereof.   
     
     
       19. An apparatus as in claim 17 additionally comprising:
 a second pair of sample and hold circuits, connected to cooperate with the first pair of sample and hold circuits, such that in a first mode, the first pair of sample and hold circuits stores respective integrated charge samples from the plus charge input and minus charge input, and such that in a second mode, the second pair of sample and hold circuits stores the plus signal charge and the minus signal charge, respectively.   
     
     
       20. An apparatus as in claim 19 wherein the difference amplifier is connected to determine the difference between the output of the first pair of sample and hold circuits in the first mode and is connected to determine a difference in the outputs between the second pair of sample and hold circuit outputs in the second mode. 
     
     
       21. An apparatus as in claim 19 wherein the difference amplifier compares a charge integrator result at a first time with a charge integrator result a second time, such that a plus charge input applied with the switch in one state is compared with the plus charge input with the switch compared in another state.