Method for fabricating semiconductor device with vertical channel transistor

Abstract

A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.

What is claimed is: 
     
       1. A method of fabricating a semiconductor memory device with a vertical channel transistor, the method comprising:
 forming a plurality of pillars on a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar and having a first hard mask pattern on the upper pillar; 
 forming a surround type gate electrode surrounding the lower pillar; 
 forming an insulation layer filling a space between the pillars; 
 forming a preliminary trench by etching the insulation layer using a second hard mask pattern for a word line, corresponding to a region where a word line is to be formed, until a portion of the upper pillar is exposed; 
 forming a buffer layer on top of the first hard mask and sidewalls of the preliminary trench; and 
 forming a trench for a word line by etching the insulation layer until a portion of the surround type gate electrode is exposed. 
 
     
     
       2. The method of  claim 1 , wherein forming the plurality of pillars comprises forming a spacer over sidewalls of the first hard mask pattern and sidewalls of the upper pillar. 
     
     
       3. The method of  claim 2 , wherein the first hard mask pattern and the spacer comprise a nitride layer. 
     
     
       4. The method of  claim 1 , wherein forming the surround type gate electrode comprises:
 recessing the lower pillar to a predetermined depth through an isotropic etch process; 
 forming a conductive layer for a gate electrode over a resultant structure; and 
 performing an etch-back process on the conductive layer until the substrate is exposed. 
 
     
     
       5. The method of  claim 4 , further comprising forming a gate dielectric layer before forming the conductive layer for the gate electrode. 
     
     
       6. The method of  claim 1 , wherein forming the insulation layer filling the space between the pillars comprises:
 forming the insulation layer over a resultant structure where the pillar and the surround type gate electrode are formed; and 
 planarizing the insulation layer until the first hard mask pattern is exposed. 
 
     
     
       7. The method of  claim 1 , wherein the insulation layer is formed of an oxide. 
     
     
       8. The method of  claim 1 , wherein the second hard mask pattern for the word line is formed of an amorphous carbon. 
     
     
       9. The method of  claim 8 , further comprising, after forming the preliminary trench, removing the second hard mask pattern using a removal process. 
     
     
       10. The method of  claim 1 , wherein forming the preliminary trench is performed until a half the upper pillar is exposed. 
     
     
       11. The method of  claim 1 , wherein forming the buffer layer on top of the first hard mask and sidewalls of the preliminary trench comprises:
 forming the buffer layer over a resultant structure after forming a preliminary trench; and 
 removing a portion of the buffer layer on a bottom of the preliminary trench. 
 
     
     
       12. The method of  claim 1 , wherein the buffer layer is formed of an insulation material. 
     
     
       13. The method of claim  11  12, wherein the buffer layer is formed of one material selected from the group consisting of ozone-undoped silicate glass (O 3 -USG), boro-phospho silicate glass (BPSG) and plasma enhanced tetra ethyl ortho silicate (PETEOS). 
     
     
       14. The method of claim  1  11, wherein removing the portion of the buffer layer is performed using wet etching. 
     
     
       15. The method of  claim 1 , further comprising:
 removing the buffer layer after forming the trench for the word line; and 
 partially filling the trench with a conductive layer to form a word line. 
 
     
     
       16. A method for fabricating a semiconductor memory device with a vertical channel transistor, the method comprising:
 forming a plurality of pillars on a substrate, each of the plurality of pillars having a first hard mask pattern;   forming an insulation layer filling a space between adjacent ones of the plurality of pillars;   forming, between the adjacent ones of the plurality of pillars, a preliminary trench by etching the insulation layer to a first depth using a second hard mask pattern corresponding to a region where a word line is to be formed;   forming a buffer layer on top of the first hard mask pattern and sidewalls of the preliminary trench; and   forming a trench by etching the insulation layer to a second depth that is greater than the first depth.    
     
     
       17. The method of claim 16, wherein forming the plurality of pillars comprises forming a spacer over sidewalls of the first hard mask pattern and an upper portion of each of the plurality of pillars.  
     
     
       18. The method of claim 17, wherein the first hard mask pattern and the spacer comprise a nitride layer.  
     
     
       19. The method of claim 16, further comprising forming a gate electrode and a gate dielectric layer for each of the plurality of pillars with the gate dielectric being located between the gate electrode and a respective pillar of the plurality of pillars.  
     
     
       20. The method of claim 16, wherein forming the insulation layer filling the space between the adjacent ones of the plurality of pillars comprises:
 forming the insulation layer over a resultant structure after forming of the plurality of pillars on the substrate; and   planarizing the insulation layer until the first hard mask pattern is exposed.    
     
     
       21. The method of claim 16, wherein the insulation layer is formed of an oxide.  
     
     
       22. The method of claim 16, wherein the second hard mask pattern is formed of an amorphous carbon.  
     
     
       23. The method of claim 22, further comprising after forming the preliminary trench, removing the second hard mask pattern using a removal process.  
     
     
       24. The method of claim 16, wherein forming the buffer layer on top of the first hard mask and sidewalls of the preliminary trench comprises:
 forming the buffer layer over a resultant structure after forming a preliminary trench; and   removing a portion of the buffer layer on a bottom of the preliminary trench.    
     
     
       25. The method of claim 16, wherein the buffer layer is formed of an insulation material.  
     
     
       26. The method of claim 25, wherein the buffer layer is formed of one material selected from the group consisting of ozone-undoped silicate glass (O 3 -USG), boro-phospho silicate glass (BPSG) and plasma enhanced tetra ethyl ortho silicate (PETEOS).  
     
     
       27. The method of claim 24, wherein removing the portion of the buffer layer is performed using wet etching.  
     
     
       28. The method of claim 16, further comprising:
 removing the buffer layer after forming the trench and   partially filling the trench with a conductive layer.