Liquid crystal display panel and manufacturing method thereof

Abstract

A liquid crystal display (LCD) panel includes pixels arranged in matrix, and first and second scan lines and a storage capacitance line. Each pixel has a first sub-pixel, which is disposed between the first and second scan lines, and first to third thin-film transistors (TFTs) and a pixel electrode divided into first and second regions. The first TFT is electrically connected to the first scan line and the first region. The second TFT is electrically connected to the first scan line and the second region. The third TFT is electrically connected to the second scan line and the second region. The storage capacitance line is electrically connected to the third TFT. A distance between the storage capacitance line and the first scan line is longer than that between the storage capacitance line and the second scan line.

What is claimed is: 
     
       1. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a first scan line disposed on the thin film transistor substrate; 
 a second scan line disposed on the thin film transistor substrate and arranged in parallel to the first scan line; 
 a plurality of pixels wherein each of the pixels comprises a first sub-pixel disposed between corresponding to the first scan line and the second scan line, and has a first thin-film transistor (TFT), a second TFT, a third TFT and a pixel electrode, the pixel electrode is divided into a first region and a second region for displaying different signals, the first TFT is electrically connected to the first scan line via a first gate and connected to the first region by a first drain electrode, the second TFT is electrically connected to the first scan line via a second gate and connected to the second region by a second drain electrode, and the third TFT is electrically connected to the second scan line via a third gate and connected to the second region by a third drain electrode; 
 a data line connecting a first source electrode of the first TFT and a second source electrode of the second TFT; and 
 a storage capacitance line electrically connected to the third TFT; 
 wherein the TFTs satisfy the formula (1):
   C gd2 >C gd1   (1),
 
 
 wherein C gd1  denotes a parasitic capacitance between the first drain electrode of the first TFT and the first scan line, and C gd2  denotes a parasitic capacitance between the second drain electrode of the second TFT and the first scan line. 
 
     
     
       2. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a first scan line disposed on the thin film transistor substrate; 
 a second scan line disposed on the thin film transistor substrate and arranged in parallel to the first scan line; 
 a plurality of pixels wherein each of the pixels comprises a first sub-pixel disposed between corresponding to the first scan line and the second scan line, and has a first thin-film transistor (TFT), a second TFT, a third TFT and a pixel electrode, the pixel electrode is divided into a first region and a second region for displaying different signals, the first TFT is electrically connected to the first scan line via a first gate and connected to the first region by a first drain electrode, the second TFT is electrically connected to the first scan line via a second gate and connected to the second region by a second drain electrode, and the third TFT is electrically connected to the second scan line via a third gate and connected to the second region by a third drain electrode; 
 a data line connecting a first source electrode of the first TFT and a second source electrode of the second TFT; and 
 a storage capacitance line electrically connected to the third TFT; 
 wherein the TFTs satisfy the formula (2):
   W 2 /L 2 >W 1 /L 2   (2),
 
 
 wherein W 1  is a channel width of the first TFT, W 2  is a channel width of the second TFT, L 1  is a channel length of the first TFT and L 2  is a channel length of the second TFT. 
 
     
     
       3. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a first scan line disposed on the thin film transistor substrate; 
 a second scan line disposed on the thin film transistor substrate and arranged in parallel to the first scan line; 
 a plurality of pixels wherein each of the pixels comprises a first sub-pixel disposed between corresponding to the first scan line and the second scan line, and has a first thin-film transistor (TFT), a second TFT, a third TFT and a pixel electrode, the pixel electrode is divided into a first region and a second region for displaying different signals, the first TFT is electrically connected to the first scan line via a first gate and connected to the first region by a first drain electrode, the second TFT is electrically connected to the first scan line via a second gate and connected to the second region by a second drain electrode, and the third TFT is electrically connected to the second scan line via a third gate and connected to the second region by a third drain electrode; 
 a data line connecting a first source electrode of the first TFT and a second source electrode of the second TFT; and 
 a storage capacitance line electrically connected to the third TFT; 
 said LCD panel further comprising:
 an opposing substrate disposed opposite to the TFT substrate and having a common electrode, wherein a first liquid crystal capacitor is formed between the common electrode and the first region of the first sub-pixel, and a second liquid crystal capacitor is formed between the common electrode and the second region of the first sub-pixel: 
 a liquid crystal layer disposed between the TFT substrate and the opposing substrate; and 
 a patterned metal layer disposed opposite to the storage capacitance line, wherein a first portion of the patterned metal layer is electrically connected to the first region to form a first storage capacitor together with the storage capacitance line, a second portion of the patterned metal layer is electrically connected to the second region and the third TFT to form a second storage capacitor together with the storage capacitance line, and a third portion of the patterned metal layer is electrically connected to the third TFT to form a first auxiliary capacitor together with the storage capacitance line and to form a second auxiliary capacitor together with the first region, 
 
 wherein region forming ratios of the first region to the second region of the first sub-pixel satisfy the formula (3):
   C st1 /C lc1 >C st2 /C lc2   (3),
 
 
 wherein C st1  denotes the first storage capacitor, C st2  denotes the second storage capacitor, C lc1  denotes the first liquid crystal capacitor, and C lc2  denotes the second liquid crystal capacitor. 
 
     
     
       4. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a first scan line disposed on the thin film transistor substrate; 
 a second scan line disposed on the thin film transistor substrate and arranged in parallel to the first scan line; 
 a plurality of pixels wherein each of the pixels comprises a first sub-pixel disposed between corresponding to the first scan line and the second scan line, and has a first thin-film transistor (TFT), a second TFT, a third TFT and a pixel electrode, the pixel electrode is divided into a first region and a second region for displaying different signals, the first TFT is electrically connected to the first scan line via a first gate and connected to the first region by a first drain electrode, the second TFT is electrically connected to the first scan line via a second gate and connected to the second region by a second drain electrode, and the third TFT is electrically connected to the second scan line via a third gate and connected to the second region by a third drain electrode; 
 a data line connecting a first source electrode of the first TFT and a second source electrode of the second TFT; and 
 a storage capacitance line electrically connected to the third TFT; 
 wherein the pixels each further comprise a second sub-pixel and a third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel are disposed adjacent one another along the first scan line, and each of the sub-pixels has a ratio R a  defined by the formula (4):
   R a =C S /(C S +C lc +C st )  (4),
 
 
 wherein C S  denotes an auxiliary capacitor of each of the sub-pixels, C lc  denotes a liquid crystal capacitor of each of the sub-pixels, and C st  denotes a storage capacitor of each of the sub-pixels. 
 
     
     
       5. The LCD panel according to  claim 4 , wherein the ratio R a  ranges from 0.1 to 0.35. 
     
     
       6. The LCD panel according to  claim 4 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a blue sub-pixel, and the ratio R a  of each of the sub-pixels satisfies the formula (5):
   R a1 =R a2 ≧R a3   (5),
 
 wherein R a1  denotes the ratio of the red pixel, R a2  denotes the ratio of the green pixel, and R a3  denotes the ratio of the blue pixel. 
 
     
     
       7. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a first scan line disposed on the thin film transistor substrate; 
 a second scan line disposed on the thin film transistor substrate; and 
 a plurality of pixels each comprising a first sub-pixel, which is disposed between corresponds to the first scan line and the second scan line, 
 wherein
 said first sub-pixel has a first thin-film transistor (TFT), a second TFT, a third TFT and a pixel electrode, 
 the pixel electrode is divided into a first region and a second region for displaying different signals, 
 the first TFT has a first gate electrically connected to the first scan line, and a first drain electrode electrically connected to the first region, 
 the second TFT has a second gate electrically connected to the first scan line, and a second drain electrode electrically connected to the second region, 
 the third TFT has a third gate electrically connected to the second scan line, and a third drain electrode electrically connected to the second region; and 
 
 a data line electrically connecting a first source electrode of the first TFT and a second source electrode of the second TFT, 
 wherein
 the first scan line overlaps a first conductive pattern, which is connected to the first drain electrode and comprises the first region of the pixel electrode, in a first overlapped area; 
 the first scan line overlaps a second conductive pattern, which is connected to the second drain electrode and comprises the second region of the pixel electrode, in a second overlapped area; and 
 both said first overlapping area and said second overlapping area are not zero and said first overlapped area is smaller than said second overlapped area. 
 
 
     
     
       8. The LCD panel according to  claim 7 , wherein the storage capacitance line is disposed between the pixel electrode and the second scan line. 
     
     
       9. The LCD panel according to  claim 7 , wherein the TFTs satisfy the formula (1):
   C gd2 ≧C gd1   (1),
 
 wherein C gd2  denotes a parasitic capacitance between the first drain electrode of the first TFT and the first scan line, and C gd2  denotes a parasitic capacitance between the second drain of the second TFT and the first scan line. 
 
     
     
       10. The LCD panel according to  claim 7 , wherein the TFTs satisfy the formula (2):
   W 2 /L 2 ≧W 1 /L 2 L 1   (2),
 
 wherein W 1  is a channel width of the first TFT, W 2  is a channel width of the second TFT, L 1  is a channel length of the first TFT and L 2  is a channel length of the second TFT. 
 
     
     
       11. The LCD panel according to  claim 7 , further comprising:
 an opposing substrate disposed opposite to the TFT substrate and having a common electrode, wherein a first liquid crystal capacitor is formed between the common electrode and the first region of the first sub-pixel, and a second liquid crystal capacitor is formed between the common electrode and the second region of the first sub-pixel; 
 a liquid crystal layer disposed between the TFT substrate and the opposing substrate; 
 a storage capacitance line formed on the TFT substrate in parallel to the first scan line and the second scan line and electrically connected to the third TFT; and 
 a patterned metal layer disposed opposite to the storage capacitance line, wherein a first portion of the patterned metal layer is electrically connected to the first region to form a first storage capacitor together with the storage capacitance line, a second portion of the patterned metal layer is electrically connected to the second region and the third TFT to form a second storage capacitor together with the storage capacitance line, and a third portion of the patterned metal layer is electrically connected to the third TFT to form a first auxiliary capacitor together with the storage capacitance line and to form a second auxiliary capacitor together with the first region; 
 wherein region forming ratios of the first region to the second region of the first sub-pixel satisfy the formula (3):
   C st1 /C lc1 >C st2 /C lc2   (3),
 
 
 wherein C st1  denotes the first storage capacitor, C st2  denotes the second storage capacitor, C lc1  denotes the first liquid crystal capacitor, and C lc2  denotes the second liquid crystal capacitor. 
 
     
     
       12. The LCD panel according to  claim 7 , wherein the pixels each further comprise a second sub-pixel and a third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel are disposed adjacent one another along the first scan line, and each of the sub-pixels has a ratio R a  defined by the formula (4):
   R a =C S /(C S +C lc +C st )  (4),
 
 wherein C S  denotes an auxiliary capacitor of each of the sub-pixels, C lc  denotes a liquid crystal capacitor of each of the sub-pixels, and C st  denotes a storage capacitor of each of the sub-pixels; and 
 wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a blue sub-pixel, and the ratio R, of each of the sub-pixels satisfies the formula (5):
   R a1 =R a2 ≧R a3   (5),
 
 
 wherein R a1  denotes the ratio of the red pixel, R a2  denotes the ratio of the green pixel, and R a3  denotes the ratio of the blue pixel. 
 
     
     
       13. A method of manufacturing a liquid crystal display (LCD) panel, the method comprising steps of:
 forming a first scan line and a second scan line on a thin-film transistor (TFT) substrate; 
 forming a first TFT and a second TFT having first and second gates electrically connected to the first scan line, and first and second drains overlapping the first scan line; 
 forming a third TFT having a third gate electrically connected to the second scan line; 
 forming a data line on the TFT substrate to electrically connect first and second sources of the first and second TFTs; 
 forming a pixel electrode on the TFT substrate and between the first scan line and the second scan line; 
 connecting the TFT substrate to an opposing substrate; and 
 forming a liquid crystal layer between the TFT substrate and the opposing substrate; 
 wherein
 the pixel electrode is divided into a first region and a second region for displaying different signals, the first drain of the first TFT is electrically connected to the first region, the second drain of the second TFT is electrically connected to the second region, and a third drain of the third TFT is electrically connected to the second region; and 
 a first non-zero overlapped area, where wherein said first scan line overlaps said first drain and said first region, is formed to be smaller than a second non-zero overlapped area, where said first scan line overlaps said second drain and said second region. 
 
 
     
     
       14. The method according to  claim 13 , further comprising a step of:
 forming a storage capacitance line on the TFT substrate, wherein the storage capacitance line is electrically connected to the third TFT, and a distance between the storage capacitance line and the first scan line is longer than a distance between the storage capacitance line and the second scan line, 
 wherein the storage capacitance line is disposed between the pixel electrode and the second scan line. 
 
     
     
       15. The method according to  claim 14 , wherein the distance between the storage capacitance line and the second scan line ranges from 4 μm to 20 μm. 
     
     
       16. The method according to  claim 14 , wherein the storage capacitance line has at least one electrical extension overlapping an edge of the pixel electrode along the data line. 
     
     
       17. The method according to  claim 14 , further comprising a step of:
 forming a patterned metal layer on the thin-film transistor (TFT) substrate and opposite to the storage capacitance line, wherein a first portion of the patterned metal layer is electrically connected to the first region to form a first storage capacitor together with the storage capacitance line, a second portion of the patterned metal layer is electrically connected to the second region and the third TFT to form a second storage capacitor together with the storage capacitance line, and a third portion of the patterned metal layer is electrically connected to the third TFT to form a first auxiliary capacitor together with the storage capacitance line and to form a second auxiliary capacitor together with the first region. 
 
     
     
       18. The method according to  claim 17 , wherein region forming ratios of the first region to the second region of the first sub-pixel satisfy the formula (3):
   C st1 /C lc1 >C st2 /C lc2   (3),
 
 wherein C st1  denotes the first storage capacitor, C st2  denotes the second storage capacitor, C lc1  denotes the to first liquid crystal capacitor, and C lc2  denotes the second liquid crystal capacitor. 
 
     
     
       19. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a plurality of scan lines disposed in parallel on the thin film transistor (TFT) substrate and including a first scan line and a second scan line;   a plurality of pixels, each of the pixels divided into a first region and a second region;   a plurality of TFTs disposed on the TFT substrate and including, for each pixel, a first TFT, a second TFT and a third TFT, wherein
 the first TFT is electrically connected to the first scan line, 
 the first TFT is electrically connected to the first region by a first drain electrode, 
 the second TFT is electrically connected to the first scan line, 
 the second TFT is electrically connected to the second region by a second drain electrode, 
 the third TFT is electrically connected to the second scan line, and 
 the third TFT is electrically connected to the second region by a third drain electrode; 
   a data line electrically connected to a first source electrode of the first TFT and a second source electrode of the second TFT; and   a storage capacitance line electrically connected to the third TFT;   wherein the TFTs satisfy the formula (1):
   C gd2 >C gd1   (1),
 
   wherein C gd1  denotes a parasitic capacitance between the first drain electrode of the first TFT and the first scan line, and C gd2  denotes a parasitic capacitance between the second drain electrode of the second TFT and the first scan line.   
     
     
       20. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a plurality of scan lines disposed in parallel on the thin film transistor (TFT) substrate and including a first scan line and a second scan line;   a plurality of pixels, each of the pixels divided into a first region and a second region;   a plurality of TFTs disposed on the TFT substrate and including, for each pixel, a first TFT, a second TFT and a third TFT, wherein the first TFT is electrically connected to the first scan line and the first region, the second TFT is electrically connected to the first scan line and the second region, and the third TFT is electrically connected to the second scan line and the second region;   a data line electrically connected to a first source electrode of the first TFT and a second source electrode of the second TFT; and   a storage capacitance line electrically connected to the third TFT;   wherein the TFTs satisfy the formula (2):
   W 2 /L 2 >W 1 /L 1   (2),
 
   wherein W 1  is a channel width of the first TFT, W 2  is a channel width of the second TFT, L 1  is a channel length of the first TFT and L 2  is a channel length of the second TFT.   
     
     
       21. A liquid crystal display (LCD) panel, comprising a thin film transistor substrate, wherein the thin film transistor substrate further comprises:
 a plurality of scan lines disposed in parallel on the thin film transistor (TFT) substrate and including a first scan line and a second scan line;   a plurality of pixels, wherein each of the pixels has a pixel electrode divided into a first region and a second region;   a plurality of TFTs disposed on the TFT substrate and including, for each pixel, a first TFT, a second TFT and a third TFT, wherein the first TFT is electrically connected to the first scan line and the first region, the second TFT is electrically connected to the first scan line and the second region, and the third TFT is electrically connected to the second scan line and the second region;   a data line electrically connected to a first source electrode of the first TFT and a second source electrode of the second TFT; and   a storage capacitance line electrically connected to the third TFT;   said LCD panel further comprising:   an opposing substrate disposed opposite to the TFT substrate and having a common electrode, wherein a first liquid crystal capacitor is formed between the common electrode and the first region of the pixel electrode, and a second liquid crystal capacitor is formed between the common electrode and the second region of the pixel electrode;   a liquid crystal layer disposed between the TFT substrate and the opposing substrate;   a first storage capacitor electrically connected to the first region of the pixel electrode;   a second storage capacitor electrically connected to the second region of the pixel electrode and the third TFT; and   a first auxiliary capacitor electrically connected to the third TFT;   wherein region forming ratios of the first region to the second region of the pixel electrode satisfy the formula (3):
   C st1 /C lc1 >C st2 /C lc2   (3),
 
   wherein C st1  denotes the first storage capacitor, C st2  denotes the second storage capacitor, C lc1  denotes the first liquid crystal capacitor, and C lc2  denotes the second liquid crystal capacitor.