Reliability unit for determining a reliability value for at least one bit decision

Abstract

A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.

We claim: 
     
       1. A reliability unit that determines a reliability value for at least one bit decision, comprising:
 one or more functional elements, wherein each of said functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. 
 
     
     
       2. The reliability unit of  claim 1 , wherein at least two of said functional units operate in series per multiple-step-trellis cycle, and wherein at least two groups of said at least two functional units operate in parallel per multiple-step-trellis cycle. 
     
     
       3. The reliability unit of  claim 1 , wherein said reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis. 
     
     
       4. The reliability unit of  claim 1 , wherein said reliability unit determines a plurality of reliability values for each multiple-step trellis cycle. 
     
     
       5. The reliability unit of  claim 1 , wherein at least two groups of said at least two functional units operate in parallel and wherein comparators in a first functional unit in each group use a first path metric difference and wherein comparators in a second functional unit in each group use a second path metric difference. 
     
     
       6. The reliability unit of  claim 1 , further comprising at least four AND gates in said functional element each operating on a different equivalence bit. 
     
     
       7. The reliability unit of  claim 1 , wherein a plurality of said functional units are configured in an array structure having a plurality of rows and a plurality of columns. 
     
     
       8. The reliability unit of  claim 7 , wherein an output of one of said functional units in a first column is applied as an input to at least one functional unit in a subsequent column. 
     
     
       9. The reliability unit of  claim 7 , wherein a first row in said array structure corresponds to reliabilities for even one-step-trellis periods and wherein a second row in said array structure corresponds to reliabilities for odd one-step-trellis periods. 
     
     
       10. The reliability unit of  claim 7 , wherein a column in said array structure corresponds to a one-step-trellis period. 
     
     
       11. The reliability unit of  claim 7 , wherein inputs to a given functional unit comprise at least one reliability value from at least one functional element of a previous column. 
     
     
       12. The reliability unit of  claim 7 , wherein an output of a prior functional unit in said array structure is compared with a path metric difference. 
     
     
       13. The reliability unit of  claim 1 , wherein said output of the comparator and said equivalence bit are applied to an AND gate that controls the multiplexer. 
     
     
       14. The reliability unit of  claim 1 , wherein a first AND gate in a first functional unit uses a first equivalence bit and a second AND gate in a second functional unit uses a second equivalence bit. 
     
     
       15. A circuit, comprising:
 one or more functional elements, wherein each of said functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and a bit control the multiplexer. 
 
     
     
       16. The circuit of  claim 15 , wherein at least two of said functional units operate in series, and wherein at least two groups of said at least two functional units operate in parallel. 
     
     
       17. The circuit of  claim 15 , wherein a plurality of said functional units are configured in an array structure having a plurality of rows and a plurality of columns. 
     
     
       18. The circuit of  claim 17 , wherein an output of one of said functional units in a first column is applied as an input to at least one functional unit in a subsequent column. 
     
     
       19. The circuit of  claim 15 , wherein said output of the comparator and said bit are applied to an AND gate that controls the multiplexer. 
     
     
       20. The circuit of  claim 15 , wherein at least two groups of said at least two functional units operate in parallel and wherein comparators in a first functional unit in each group use a first value and wherein comparators in a second functional unit in each group use a second value. 
     
     
       21. The circuit of  claim 15 , further comprising at least four AND gates in said functional element each operating on a different bit. 
     
     
       22. The circuit of  claim 17 , wherein inputs to a given functional unit comprise at least one value from at least one functional element of a previous column. 
     
     
       23. The circuit of  claim 17 , wherein an output of a prior functional unit in said array structure is compared with a path metric difference. 
     
     
       24. The circuit of  claim 15 , wherein said output of the comparator and said bit are applied to an AND gate that controls the multiplexer. 
     
     
       25. The circuit of  claim 15 , wherein a first AND gate in a first functional unit uses a first bit and a second AND gate in a second functional unit uses a second bit.