Semiconductor memory device and driving method thereof

Abstract

A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

What is claimed is: 
     
       1. A semiconductor memory device system, comprising:
 a variable delay configured to delay a clock; 
 an output driver configured to transfer data to a chipset in response to a calibration command received from the chipset and the delayed clock; 
 an output buffer configured to transfer a data strobe signal to the chipset in response to the calibration command and the delayed clock; and 
 a calibration controller configured to control the delay time of the variable delay according to an output AC parameters parameter measured by the chipset. 
 
     
     
       2. The semiconductor memory device system of  claim 1 , wherein the output driver comprises:
 a pre-driver configured to pre-drive an output data signal; and 
 a main driver configured to drive a data output terminal in response to an output signal of the pre-driver. 
 
     
     
       3. The semiconductor memory device system of  claim 1 , wherein the output AC parameters include at least parameter is a selected one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and a clock, and a parameter representing skew between the data and the clock. 
     
     
       4. A semiconductor memory device system, comprising:
 a variable delay configured to delay a clock; 
 an output driver configured to receive and output data in response to the delayed clock; and 
 a calibration controller configured to measure an AC parameters parameter of data and data strobe signal received from a chipset in response to a calibration command received from the chipset, and control the delay time of the variable delay according to measured values of the output AC parameters parameter. 
 
     
     
       5. The semiconductor memory device system of  claim 4 , wherein the calibration controller comprises:
 a feedback input buffer configured to feed back the data and the data strobe signal, which are transferred to the chipset, in response to a calibration test mode signal generated when the calibration command is received; and 
 a timing measurer configured to receive the data and the data strobe signal from the feedback input buffer, measure the AC parameters parameter of data and data strobe signal, and control the delay time of the variable delay according to measured values of the output AC parameters parameter. 
 
     
     
       6. The semiconductor memory device system of  claim 4 , wherein the calibration controller comprises:
 a real-time monitor configured to monitor the data and the data strobe signal being transferred to the chipset; and 
 a timing measurer configured to receive the data and the data strobe signal from the real-time monitor, measure the AC parameters parameter of data and data strobe signal, and control the delay time of the variable delay according to measured values of the output AC parameters parameter. 
 
     
     
       7. The semiconductor memory device system of  claim 4 , wherein the output driver comprises:
 a pre-driver configured to pre-drive an output data signal; and 
 a main driver configured to drive a data output terminal in response to an output signal of the pre-driver. 
 
     
     
       8. The semiconductor memory device system of  claim 4 , wherein the output AC parameters include at least parameter is a selected one of a parameter representing skew between the data strobe signal and the data, a parameter representing skew between the data strobe signal and the clock, and a parameter representing skew between the data and the clock. 
     
     
       9. A method for driving a semiconductor memory device system, comprising:
 receiving a calibration command from a chipset; 
 transferring a first data and a first data strobe signal to the chipset in response to the calibration command; 
 receiving a measured values value of an output AC parameters parameter from the chipset, wherein the measured values value of an output AC parameters are parameter is measured at the chipset by using the first data and the first data strobe signal; 
 setting a delay value with respect to a clock in response to the measured values of the output AC parameters parameter; 
 delaying the clock by the delay value to output a delayed clock; and 
 transferring a second data and a second data strobe signal having a calibrated output AC parameters parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in response to the clock. 
 
     
     
       10. The method of  claim 9 , further comprising:
 after transferring the second data and the second data strobe signal, remeasuring the output AC parameters parameter at the chipset based on the second data and the second data strobe signal having the calibrated output AC parameters parameter; and 
 when the remeasured output AC parameters parameter comply with a specification, completing a calibration operation. 
 
     
     
       11. A method for driving a semiconductor memory device system, comprising:
 receiving a calibration command from a chipset; 
 receiving a first data and a first data strobe signal from the chipset; 
 measuring an AC parameters parameter of the first data and the first data strobe signal in response to the calibration command; 
 controlling the delay time of a clock according to measured values of the AC parameters parameter; and 
 transferring a second data and a second data strobe signal having a calibrated output AC parameters parameter to the chipset in response to the delayed clock and transferring a second data strobe signal to the chipset in response to the clock. 
 
     
     
       12. The memory system of claim 1, wherein the memory system is a synchronous memory system. 
     
     
       13. The memory system of claim 1, wherein the memory system is a synchronous DDR memory system. 
     
     
       14. The memory system of claim 1, further comprising a DLL configured to provide the clock. 
     
     
       15. The memory system of claim 1, further comprising a plurality of output drivers configured to transfer data to a chipset in response to a calibration command received from the chipset. 
     
     
       16. The memory system of claim 15, further comprising a plurality of variable delays corresponding to respective output drivers configured to delay the clock in response to the calibration controller to control the delay time of the plurality of variable delays according to the output AC parameter measured by the chipset. 
     
     
       17. The memory system of claim 15, wherein the output AC parameter measured by the chipset is a parameter representing skew between two signals. 
     
     
       18. The memory system of claim 17, wherein the output AC parameter measured by the chipset is a selected one of a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock, and a skew between data and the system clock. 
     
     
       19. The memory system of claim 4, wherein the memory system is a synchronous memory system. 
     
     
       20. The memory system of claim 4, wherein the memory system is a synchronous DDR memory system. 
     
     
       21. The memory system of claim 4, further comprising a DLL configured to provide the clock. 
     
     
       22. The memory system of claim 4, further comprising a plurality of output drivers configured to transfer data to a chipset in response to a calibration command received from the chipset. 
     
     
       23. The memory system of claim 22, further comprising a plurality of variable delays corresponding to respective output drivers configured to delay the clock in response to the calibration controller to control the delay time of the plurality of variable delays according to the output AC parameter measured by the chipset. 
     
     
       24. The memory system of claim 22, wherein the output AC parameter measured by the chipset is a parameter representing skew between two signals. 
     
     
       25. The memory system of claim 24, wherein the output AC parameter measured by the chipset is a selected one of a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock, and a skew between data and the system clock. 
     
     
       26. The method of claim 9, wherein the memory system is a synchronous memory system. 
     
     
       27. The method of claim 9, wherein the memory system is a synchronous DDR memory system. 
     
     
       28. The method of claim 9, wherein setting a delay value with respect to a clock comprises setting a delay value with respect to a DLL. 
     
     
       29. The method of claim 9, wherein:
 transferring a first data and a first data strobe signal to the chipset comprises transferring a plurality of first data and first data strobe signals to the chipset; and   receiving a measured value of an output AC parameter from the chipset comprises receiving a plurality of measured values of output AC parameters from the chipset corresponding to the plurality of first data and first data strobe signals.   
     
     
       30. The method of claim 29, wherein:
 setting a delay value with respect to a clock in response to the measured values of the output AC parameter comprises setting a plurality of delay values with respect to the clock in response to the measured values of the output AC parameters corresponding to the plurality of first data and first data strobe signals; and   delaying the clock by the delay value to output a delayed clock comprises delaying the clock by the plurality of delay values to output a plurality of delayed clocks corresponding to the plurality of first data and first data strobe signals.   
     
     
       31. The method of claim 29, wherein receiving a measured value of an output AC parameter from the chipset comprises receiving a parameter representing skew between two signals. 
     
     
       32. The method of claim 31, wherein the output AC parameter measured by the chipset is a selected one of a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock, and a skew between data and the system clock. 
     
     
       33. The method of claim 11, wherein the memory system is a synchronous memory system. 
     
     
       34. The method of claim 11, wherein the memory system is a synchronous DDR memory system. 
     
     
       35. The method of claim 11, wherein controlling the delay time of a clock comprises controlling the delay time of a DLL. 
     
     
       36. The method of claim 11, wherein:
 receiving a first data and a first data strobe signal from the chipset comprises receiving a plurality of first data and first data strobe signals from the chipset; and   measuring an AC parameter of the first data and the first data strobe signal in response to the calibration command comprises measuring a plurality of AC parameters corresponding to the plurality of first data and first data strobe signals.   
     
     
       37. The method of claim 36, wherein controlling the delay time of a clock according to measured values of the AC parameter comprises controlling a plurality of delay times of a clock in response to the measured values of the AC parameters corresponding to the plurality of first data and first data strobe signals. 
     
     
       38. The method of claim 36, wherein measuring an AC parameter of the first data and the first data strobe signal in response to the calibration command comprises measuring a parameter representing skew between two signals. 
     
     
       39. The method of claim 38, wherein the measured AC parameter is a selected one of a skew between the data strobe signal and the data, a skew between the data strobe signal and a system clock, and a skew between data and the system clock.