Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size

Abstract

A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

What is claimed is: 
     
       1. A semiconductor integrated circuit device, comprising:
 a semiconductor chip having a memory cell array region and a peripheral circuit region surrounding the memory cell array region; 
 a plurality of bonding pads disposed on only one a first side of the semiconductor chip on the peripheral circuit region; and 
 a plurality of leads formed on both the one side of the semiconductor chip on which the bonding pads are disposed and a second side of the semiconductor chip opposite the first side on which the bonding pads are disposed for connection with the bonding pads; 
 the plurality of leads including a first leads group on the first side of the semiconductor chip on which the bonding pads are disposed and a second leads group on the second side of the semiconductor chip opposite the first side on which the bonding pads are disposed; 
 a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads; 
 wherein the first plurality of bonding wires only cross the peripheral circuit region and; 
 wherein the second plurality of bonding wires or the second plurality of bonding wires and the second leads group cross the memory cell array region. 
 
     
     
       2. The device of  claim 1 , wherein the plurality of bonding pads are disposed in at least one row. 
     
     
       3. The device of  claim 2 , wherein the plurality of bonding pads are disposed in two rows. 
     
     
       4. The device of  claim 1 , further comprising:
 a plurality of bonding wires electrically connecting the plurality of leads, respectively, with a portion of the bonding pads so as to cross the memory cell array region.   
     
     
       5. A semiconductor integrated circuit device, comprising:
 a semiconductor chip having a memory cell array region and a peripheral circuit region surrounding the memory cell array region; 
 a plurality of bonding pads disposed in at least one row on only one a first side of the semiconductor chip on the peripheral circuit region; 
 a first leads group disposed adjacent to the bonding pad first side of the semiconductor chip; 
 a second leads group disposed opposite the first leads group; and 
 a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads; 
 wherein the first plurality of bonding wires only cross the peripheral circuit region and; 
 wherein the second plurality of bonding wires or the second plurality of bonding wires and the second leads group cross the memory cell array region. 
 
     
     
       6. The device of  claim 5 , wherein the second leads group disposed opposite the first leads group are located to a second side of the semiconductor chip opposite the bonding pad first side. 
     
     
       7. The device of  claim 5 , wherein the plurality of bonding pads are electrically connected alternately with the first leads group and the second leads group by the first plurality of bonding wires and the second plurality of bonding wires, respectively, the first plurality of bonding wires being disposed over the peripheral circuit region, the second plurality of bonding wires being disposed over the memory cell array region. 
     
     
       8. The device of  claim 5 , wherein the plurality of bonding pads are disposed in a first row and a second row, the first row of bonding pads and the second row of bonding pads being electrically connected to the first leads group and the second leads group, respectively, by the first plurality of bonding wires and the second plurality of bonding wires, the first plurality of bonding wires being disposed over the peripheral circuit region, and the second plurality of bonding wires being disposed over the memory cell array region. 
     
     
       9. The device of  claim 5 , wherein the second leads group extends over a portion of the semiconductor chip region. 
     
     
       10. The device of  claim 9 , A semiconductor integrated circuit device, comprising:
 a semiconductor chip having a memory cell array region and a peripheral circuit region surrounding the memory cell array region; 
 a plurality of bonding pads disposed in at least one row on only a first side of the semiconductor chip on the peripheral circuit region; 
 a first leads group disposed adjacent to the first side of the semiconductor chip; 
 a second leads group disposed opposite the first leads group; and 
 a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads; 
 wherein the first plurality of bonding wires only cross the peripheral circuit region and; 
 wherein the second plurality of bonding wires or the second plurality of bonding wires and the second leads group cross the memory cell array region, wherein the plurality of bonding pads are electrically connected alternately with the first leads group and the second leads group by the first plurality of bonding wires and the second plurality of bonding wires, respectively, the first plurality of bonding wires being disposed over the peripheral circuit region, the second plurality of bonding wires being disposed over the memory cell array region. 
 
     
     
       11. The device of  claim 9 , A semiconductor integrated circuit device, comprising:
 a semiconductor chip having a memory cell array region and a peripheral circuit region surrounding the memory cell array region; 
 a plurality of bonding pads disposed in at least one row on only a first side of the semiconductor chip on the peripheral circuit region; 
 a first leads group disposed adjacent to the first side of the semiconductor chip; 
 a second leads group disposed opposite the first leads group; and 
 a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads; 
 wherein the first plurality of bonding wires only cross the peripheral circuit region and; 
 wherein the second plurality of bonding wires or the second plurality of bonding wires and the second leads group cross the memory cell array region, wherein the plurality of bonding pads are disposed in a first row and a second row, the first row of bonding pads and a second row of bonding pads being electrically connected to the first leads group and the second leads group, respectively, by the first plurality of bonding wires and the second plurality of bonding wires, the first plurality of bonding wires being disposed over the peripheral circuit region, and the second plurality of bonding wires being disposed over the memory cell array region. 
 
     
     
       12. A semiconductor integrated circuit device, comprising:
 a semiconductor chip having a memory cell array region; 
 a plurality of bonding pads disposed on only one a first side of the semiconductor chip; and 
 a plurality of leads formed on both the first side of the semiconductor chip on which the bonding pads are disposed and a second side of the semiconductor chip opposite the one first side on which the bonding pads are disposed for connection with the bonding pads; 
 the plurality of leads including a first leads group on the first side of the semiconductor chip on which the bonding pads are disposed and a second leads group on the second side of the semiconductor chip opposite the first side on which the bonding pads are disposed; 
 a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads; 
 wherein the first plurality of bonding wires do not cross the memory cell array region and; 
 wherein the second plurality of bonding wires or the second plurality of bonding wires and the second leads group cross the memory cell array region. 
 
     
     
       13. The device of  claim 12 , further comprising:
 a plurality of bonding wires electrically connecting the plurality of leads to corresponding bonding pads disposed on the one side so as to cross the memory cell array region.   
     
     
       14. The device of  claim 12 , wherein the plurality of bonding pads are disposed in at least one row. 
     
     
       15. The device of  claim 14 , wherein the plurality of bonding pads are disposed in two rows. 
     
     
       16. The device of  claim 12 , wherein
 the semiconductor chip includes a peripheral circuit region surrounding the memory cell array region, and 
 the bonding pads are disposed on the one first side of the semiconductor chip on the peripheral circuit region. 
 
     
     
       17. A semiconductor integrated circuit device, comprising:
 a semiconductor chip having a memory cell array region and a peripheral circuit region on a front surface of the semiconductor chip, the front surface including a first side and a second side opposite to the first side;   a plurality of bonding pads disposed in the peripheral circuit region, the bonding pads being adjacent to and along only the first side;   a first leads group adjacent to the first side;   a second leads group adjacent to the second side; and   a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads;   wherein the plurality of bonding pads include a first bonding pads group and a second bonding pads group, the first bonding pads group is connected to the first leads group by the first plurality of bonding wires and the second bonding pads group is connected to the second leads group by the second plurality of bonding wires, respectively; and   wherein the first bonding pads group is only on a first region of the peripheral circuit region and the second bonding pads group is only on a second region of the peripheral circuit region, the first region is separated from the second region by a space.    
     
     
       18. The device of claim 17, wherein the second leads group is opposite the first leads group.  
     
     
       19. The device of claim 17, wherein the second leads group is located to a side of the semiconductor chip opposite the bonding pad side.  
     
     
       20. The device of claim 17, wherein the plurality of bonding pads are electrically connected alternately with the first leads group and the second leads group by the first plurality of bonding wires and the second plurality of bonding wires, respectively.  
     
     
       21. The device of claim 17, wherein the plurality of bonding pads are in a first row and a second row, the first row of bonding pads and the second row of bonding pads being electrically connected to the first leads group and the second leads group, respectively, by the first plurality of bonding wires and the second plurality of bonding wires.  
     
     
       22. The device of claim 17, wherein the second leads group extends over a portion of the semiconductor chip.  
     
     
       23. The device of claim 22, wherein the plurality of bonding pads are electrically connected alternately with the first leads group and the second leads group by the first plurality of bonding wires and the second plurality of bonding wires, respectively, the first plurality of bonding wires being over the peripheral circuit region, the second plurality of bonding wires being over at least a portion of the memory cell array region.  
     
     
       24. The device of claim 22, wherein the plurality of bonding pads are in a first row and a second row, the first row of bonding pads and a second row of bonding pads being electrically connected to the first leads group and the second leads group, respectively, by the first plurality of bonding wires and the second plurality of bonding wires, the first plurality of bonding wires being over the peripheral circuit region, and the second plurality of bonding wires being over at least a portion of the memory cell array region.  
     
     
       25. The device of claim 17, wherein at least one of the first and second leads groups extends across the semiconductor chip.  
     
     
       26. The device of claim 17, wherein only the first plurality of bonding wires extend across a side of the semiconductor chip.  
     
     
       27. The device of claim 17, wherein the front surface further comprises a third side and a fourth side opposite to the third side, the first side is longer than the third side.  
     
     
       28. The device of claim 27, wherein the second leads group extends over a portion of the semiconductor chip.  
     
     
       29. The device of claim 28, wherein one end of each lead of the second leads group is adjacent to and outside of the semiconductor chip and the other end of each lead of the second leads group is adjacent to the first side.