Serially decoded digital device testing

Abstract

Testing of memories that decode a serial stream of address data to access the memory may be performed by cither successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.

I claim: 
     
       1. A method of testing a memory, said memory addressed using a serial decoder, said method comprising:
 (a) simultaneously writing into all of the words in said memory; 
 (b) simultaneously writing into half of said words in said memory; 
 (c) simultaneously reading half of said words in said memory; and 
 (d) simultaneously reading the words in said memory not read in (c). 
 
     
     
       2. The method as in  claim 1 , wherein in (b), said half of said words in said memory correspond to either the even words in said memory or to the odd words in said memory. 
     
     
       3. The method as in  claim 1 , wherein half of said half of said words in said memory read in (c) are not in the set of said half of said words in said memory written in (b). 
     
     
       4. The method as in  claim 1 , wherein:
 said words in (a) are selected by resetting said serial decoder; 
 said words in (b) are selected by partial addressing of said serial decoder; 
 said words in (c) are selected by rotating a decoded address within said serial decoder; and 
 said words in (d) are selected by resetting, partially addressing, and rotating a decoded address within said serial decoder. 
 
     
     
       5. The method as in  claim 1 , wherein at least one said simultaneously reading includes simultaneously determining if voltage levels of all outputs of the words in said memory that are to be read are between two reference voltages. 
     
     
       6. The method as in  claim 5 , wherein said two reference voltages are determined by a state of a test input. 
     
     
       7. A method of isolating a single fault in a memory addressed using a serial decoder, said method comprising:
 i) testing said memory, said testing method further comprising:
 (a) simultaneously writing into all of the words in said memory, 
 (b) simultaneously writing into half of said words in said memory, 
 (c) selecting another half of said words in said memory, 
 (d) simultaneously reading said selected words from said memory, and 
 (e) repeating steps (c) and (d) until all words in said memory have been read; 
 
 ii) collecting faulty and good results from said testing said memory; 
 iii) finding results that match said faulty and good results in a fault dictionary; and 
 iv) retrieving the single fault address. 
 
     
     
       8. A semiconductor component comprising:
 one or more devices; 
 at least one test input; and 
 at least one test output; 
 wherein, in a first mode of said test input, said test output indicates if the voltage on a data input to the semiconductor component is between a first pair of predefined voltage limits, and in a second mode of said test input, said test output indicates if the voltage on said data input is not between a second pair of predefined voltage limits. 
 
     
     
       9. The semiconductor component as in  claim 8 , wherein said first mode is a normal mode, wherein in the normal mode, said test output indicates a fault if said voltage on said data input to the semiconductor component is between said first pair of predefined voltage limits; and wherein said second mode is a test mode, wherein in the test mode, said test output indicates a fault if said voltage on said data input is not between said second pair of predefined voltage limits. 
     
     
       10. The semiconductor component as in  claim 8 , wherein said first pair of predefined voltage limits equal said second pair of predefined voltage limits. 
     
     
       11. A structure for testing a plurality of functional blocks within an integrated circuit, said functional blocks comprising at least one enable input and at least one block test output, said test structure comprising:
 output logic with a test output and a plurality of inputs coupled to at least one block test output of at least one of said functional blocks; and 
 a serial decoder with one or more word lines coupled to one or more of said enable inputs of said functional blocks; 
 wherein each of said block test outputs is to be enabled by at least one of said word lines. 
 
     
     
       12. The structure as in  claim 11 , wherein said output logic is to translate values on said plurality of inputs to a fault indication on said test output of said output logic. 
     
     
       13. The structure as in  claim 12 , wherein said output logic is to translate values on each of said plurality of inputs to each of a plurality of data outputs. 
     
     
       14. The structure as in  claim 11 , wherein said output logic is to translate values on each of said plurality of inputs to each of a plurality of data outputs. 
     
     
       15. An integrated circuit comprising
 a memory; and   output logic coupled to the memory, wherein the output logic includes:
 a test input line; 
 a test output line; and 
 a plurality of output logic blocks coupled to receive, in parallel, respective bits of a word from the memory; 
   wherein the test input line is coupled to the output logic blocks to indicate whether or not the output logic is in a test mode;   wherein, if the output logic is in the test mode, a respective one of the output logic blocks is configured to cause a value indicating a fault to be output on the test output line if the respective output logic block detects a fault;   wherein if the output logic is not in the test mode, a respective one of the output logic blocks is configured to cause a value indicating an invalid signal to be output on the test output line if the respective output logic block detects an invalid signal;   wherein the fault and the invalid signal correspond to different conditions.   
     
     
       16. The integrated circuit of claim 15, wherein, the invalid signal, if the output logic is not in the test mode, corresponds to a voltage value on a respective data input line that falls within a predetermined range of voltage values lying between voltages values corresponding to logical zero and logical one. 
     
     
       17. The integrated circuit of claim 15, wherein the fault, if the output logic is in test mode, corresponds to a voltage value on a respective data input line that falls outside a predetermined range of voltage values lying between voltage values corresponding to logical zero and logical one. 
     
     
       18. A method of testing a memory, comprising:
 (a) simultaneously writing into all of the words in the memory;   (b) simultaneously writing into half of the words in the memory;   (c) simultaneously reading half of the words in the memory; and   (d) simultaneously reading the words in the memory not read in (c).   
     
     
       19. The method of claim 18, wherein in (b), the half of the words in the memory correspond to either the even words in the memory or to the odd words in the memory. 
     
     
       20. The method of claim 18, wherein half of the half of the words in the memory read in (c) are not in the set of the half of the words in the memory written in (b). 
     
     
       21. The method of claim 18, wherein at least one said simultaneously reading includes simultaneously determining if voltage levels of all outputs of the words in the memory that are to be read are between two reference voltages. 
     
     
       22. The method of claim 21, wherein the two reference voltages are determined by a state of a test input. 
     
     
       23. A method of isolating a single fault in a memory, said method comprising:
 testing the memory, wherein said testing include:
 (a) simultaneously writing into all of the words in the memory, 
 (b) simultaneously writing into half of the words in the memory, 
 (c) selecting another half of the words in the memory, 
 (d) simultaneously reading the selected words from the memory, and 
 (e) repeating steps (c) and (d) until all words in the memory have been read; 
   collecting faulty and good results from said testing the memory;   finding results that match the faulty and good results in a fault dictionary; and   retrieving an address of the single fault.   
     
     
       24. The method as in claim 23, wherein in (b), the half of the words in the memory correspond to either the even words in the memory or to the odd words in the memory. 
     
     
       25. The method as in claim 23, wherein:
 the words in (a) are selected by resetting a serial decoder configured to address the memory; and   the words in (b) are selected by partial addressing of the serial decoder.