Dynamic performance adjustment of computation means

Abstract

A dynamic performance circuit adjustment system and method that flexibly adjusts the performance of a logic circuit. The dynamic performance circuit adjustment system and method facilitates flexible power conservation. In one exemplary implementation, a dynamic performance adjustment control circuit controls performance adjustments to a logic circuit (e.g., a processor) and adjusts support functions for the logic circuit. The logic circuit performs operational functions (e.g., processing) or tasks that have different performance requirements. For example, some tasks performed by the logic circuit are required to be performed in a relatively short duration of time and other tasks performed by logic circuit have relatively longer time limitations. The dynamic performance adjustment control circuit adjusts the clock frequency and voltage at which the logic circuit operates to a relatively greater frequency and voltage for tasks required to be performed in a shorter duration of time and adjusts the frequency and voltage at which the logic circuit operates to a relatively lower frequency and voltage for tasks with longer timing tolerances. The dynamic performance adjustment system and method includes provisions to manage a transition in performance and support functions in a manner that reduces the risk of spurious signals or “glitches.”

What is claimed is: 
     
       1. A dynamic performance circuit adjustment system comprising:
 a functional circuit for performing operational tasks that have differing minimum performance and support function requirements; and   a dynamic performance adjustment control circuit for controlling performance adjustments to said functional circuit and adjustments to support functions for said functional circuit, said dynamic performance adjustment control circuit coupled to said functional circuit, wherein said dynamic performance adjustment control circuit:
 a) adjusts the frequency and voltage at which said functional circuit operates to a relatively greater frequency and voltage for tasks required to be performed in a shorter duration of time, 
 b) adjusts the frequency and voltage at which said functional circuit operates to a relatively lower frequency and voltage for tasks with longer timing tolerance, and 
 c) transmits an operation control signal to said functional circuit directing said functional circuit to cease operations for a period of time sufficient to permit said dynamic performance adjustment control circuit to make changes to said performance input signal and said support signal and permit the system to stabilize. 
   
     
     
       2. The dynamic performance circuit adjustment system of  claim 1  wherein said dynamic performance adjustment control circuit receives a performance indication signal indicating said minimal performance requirements of said functional circuit for a particular one of said tasks. 
     
     
       3. The dynamic performance circuit adjustment system of  claim 2  wherein said dynamic performance adjustment control circuit makes an adjustment to a performance signal and a support signal for said functional circuit in accordance with said performance indication signal indicating. 
     
     
       4. The dynamic performance circuit adjustment system of  claim 1  wherein said dynamic performance adjustment control circuit stops a clock signal to said functional circuit and sets a power supply signal to said functional circuit at zero volts when said functional circuit is not actively performing operation. 
     
     
       5. The dynamic performance circuit adjustment system of  claim 1  wherein said functional circuit signals said dynamic performance adjustment control circuit to adjust performance and support functions for said functional circuit and said functional circuit ceases active operation for a period of time sufficient to permit said dynamic performance adjustment control circuit to make changes to said performance input signal and said support signal and permit the system to stabilize. 
     
     
       6. A dynamic performance circuit adjustment system implemented in a palm computer system comprising;
 a logic circuit for performing operational functions or tasks;   a clock circuit for supplying a clock signal to said logic circuit, said clock circuit coupled to said logic circuit;   a voltage supply circuit for supplying a power signal to said logic circuit, said voltage supply circuit coupled to said logic circuit; and   a main dynamic adjustment control circuit for controlling the performance of said logic circuit by varying a frequency of said clock signal and by varying the voltage of said power signal, wherein said main dynamic adjustment control circuit signals said logic circuit to cease active operations for a period of time sufficient to permit said dynamic performance adjustment control circuit to make changes to said frequency and said voltage and and permit the system to stabilize, said main dynamic adjustment control circuit coupled to said logic circuit.   
     
     
       7. The dynamic performance circuit adjustment system of  claim 6  wherein said clock circuit further comprises:
 a high frequency output for supplying a first relatively high frequency signal; and 
 a low frequency output for supplying a second relatively low frequency signal. 
 
     
     
       8. The dynamic performance circuit adjustment system of  claim 6  wherein said voltage supply circuit further comprises:
 a high voltage output for supplying a first relatively high voltage signal; and 
 a low voltage output for supplying a first relatively low voltage signal. 
 
     
     
       9. The dynamic performance circuit adjustment system of  claim 6  wherein said main dynamic adjustment control circuit selectively enables a high frequency output via a high frequency enable signal and a low frequency output via a low frequency enable signal. 
     
     
       10. The dynamic performance circuit adjustment system of  claim 6  wherein said main dynamic adjustment control circuit selectively enables a high voltage output via a high voltage enable signal and a low voltage output via a low voltage enable signal. 
     
     
       11. The dynamic performance circuit adjustment system of  claim 6  wherein said performance adjustment control circuit disables a clock signal and a power signal to logic circuit. 
     
     
       12. A dynamic performance circuit adjustment method comprising the steps of:
 a) accessing a performance indication signal;   b) based upon said performance indication signal, dynamically determining a voltage level and a clock frequency;   c) supplying said voltage level and said clock frequency to said functional circuit to dynamically adjust its performance level and directing functional operations to cease for a period of time sufficient to permit stabilize before adjusting said performance level;   d) performing a task using said factional circuit; and   e) repeating steps a) through d).   
     
     
       13. A method of  claim 12  further comprising the step of ceasing functional circuit active operation during stabilization period. 
     
     
       14. A method of  claim 12  further comprising the steps of:
 c1) selecting a first relatively high frequency clock output; and 
 c2) selecting a second relatively low frequency clock output. 
 
     
     
       15. A dynamic performance circuit adjustment method of  claim 12  wherein step c) further comprises the step of switching between a low frequency source and a high frequency source. 
     
     
       16. A method of  claim 12  wherein step c) further comprises the steps of:
 enabling a first relatively high voltage signal output; and 
 enabling a second relatively low voltage signal output. 
 
     
     
       17. A method of  claim 12  wherein step c) further comprises the step of switching between a low voltage source and a high voltage source. 
     
     
       18. A dynamic performance adjustment system comprising:
 a display operable to display information thereon;   a memory device;   a functional circuit for performing operational tasks that have differing minimum frequency and voltage requirements; and   a dynamic performance adjustment control circuit for controlling at least one of frequency adjustment and voltage adjustment to said functional circuit, said dynamic performance adjustment control circuit coupled to said functional circuit, wherein said dynamic performance adjustment control circuit:
 a) adjusts at least one of frequency and voltage at which said functional circuit operates to at least one of a relatively greater frequency and a relatively greater voltage for tasks required to be performed in a shorter duration of time, 
 b) adjusts at least one of frequency and voltage at which said functional circuit operates to at least one of a relatively lower frequency and a relatively lower voltage for tasks with longer timing tolerance, and 
 c) transmits an operation control signal to said functional circuit directing said functional circuit to cease operations for a period of time sufficient to implement a change to said frequency and said voltage supplied to said functional circuit, said period of time permitting said dynamic performance adjustment control circuit to control at least one of frequency adjustment and voltage adjustment to said functional circuit and permitting said dynamic performance adjustment system to stabilize. 
   
     
     
       19. The dynamic performance adjustment system of claim 18, wherein said period of time is sufficient to permit said dynamic performance adjustment control circuit to control both frequency adjustment and voltage adjustment to said functional circuit. 
     
     
       20. The dynamic performance adjustment system of claim 18, wherein said dynamic performance adjustment control circuit receives a performance indication signal indicating a minimal performance requirement of said functional circuit for a particular one of said operational tasks. 
     
     
       21. The dynamic performance adjustment system of claim 20, wherein said dynamic performance adjustment control circuit controls at least one of frequency adjustment and voltage adjustment to said functional circuit in accordance with said performance indication signal. 
     
     
       22. The dynamic performance adjustment system of claim 18, wherein said dynamic performance adjustment control circuit stops a clock signal to said functional circuit and sets a power supply signal to said functional circuit at substantially zero volts when said functional circuit is not actively performing an operation. 
     
     
       23. The dynamic performance adjustment system of claim 18, wherein said functional circuit signals said dynamic performance adjustment control circuit to control at least one of frequency adjustment and voltage adjustment for said functional circuit, and wherein said functional circuit ceases operation for a period of time sufficient to permit said dynamic performance adjustment control circuit to control at least one of frequency adjustment and voltage adjustment to said functional circuit and permit the dynamic performance adjustment system to stabilize. 
     
     
       24. The dynamic performance adjustment system of claim 18, further comprising a bus. 
     
     
       25. The dynamic performance adjustment system of claim 24, wherein said memory device is coupled to said bus. 
     
     
       26. The dynamic performance adjustment system of claim 25, wherein said dynamic performance adjustment control circuit is coupled to said bus. 
     
     
       27. The dynamic performance adjustment system of claim 18, further comprising an input device. 
     
     
       28. The dynamic performance adjustment system of claim 18, further comprising a communication device for communicating signals. 
     
     
       29. The dynamic performance adjustment system of claim 18, further comprising a power source. 
     
     
       30. A mobile computer system comprising:
 a display for displaying information;   a memory unit;   a logic circuit for performing operational functions or tasks;   a clock circuit for supplying a clock signal to said logic circuit, said clock circuit coupled to said logic circuit;   a voltage supply circuit for supplying a power signal to said logic circuit, said voltage supply circuit coupled to said logic circuit; and   a dynamic adjustment control circuit for controlling the performance of said logic circuit by varying at least one of a frequency of said clock signal and a voltage of said power signal to said logic circuit, wherein said dynamic adjustment control circuit signals said logic circuit to cease active operations for a period of time sufficient to implement a change to said frequency and said voltage supplied to said logic circuit, said period of time permitting said dynamic adjustment control circuit to vary at least one of said frequency of said clock signal and said voltage of said power signal and permitting the mobile computer system to stabilize, said dynamic adjustment control circuit being coupled to said logic circuit.   
     
     
       31. The mobile computer system of claim 30, wherein said clock circuit further comprises: a high frequency output for supplying a high frequency signal; and a low frequency output for supplying a low frequency signal. 
     
     
       32. The mobile computer system of claim 31, wherein said voltage supply circuit further comprises: a high voltage output for supplying a high voltage signal; and a low voltage output for supplying a low voltage signal. 
     
     
       33. The mobile computer system of claim 32, wherein said dynamic adjustment control circuit selectively enables said high frequency output via a high frequency enable signal and said low frequency output via a low frequency enable signal. 
     
     
       34. The mobile computer system of claim 33, wherein said dynamic adjustment control circuit selectively enables said high voltage output via a high voltage enable signal and said low voltage output via a low voltage enable signal. 
     
     
       35. The mobile computer system of claim 30, wherein said dynamic adjustment control circuit disables said clock signal and said power signal to said logic circuit. 
     
     
       36. The mobile computer system of claim 30, further comprising an input device for receiving user input. 
     
     
       37. The mobile computer system of claim 30, further comprising a communication device for communicating signals. 
     
     
       38. The mobile computer system of claim 30, further comprising a power source. 
     
     
       39. A method comprising:
 a) accessing a performance indication signal within a computer system including a display, a memory unit, and a functional circuit;   b) based upon said performance indication signal, dynamically determining at least one of a voltage level and a clock frequency for said functional circuit;   c) supplying at least one of said voltage level and said clock frequency to said functional circuit to dynamically adjust a performance level for said functional circuit and directing said functional circuit to cease functional operations for a period of time sufficient to implement a change to said voltage level and said clock frequency supplied to said functional circuit, said period of time permitting stabilization before adjustment of said performance level;   d) performing a task using said functional circuit; and   e) repeating said a) through d).   
     
     
       40. The method of claim 39, wherein said c) comprises:
 enabling one of a high frequency clock output and a low frequency clock output.   
     
     
       41. The method of claim 39, wherein said c) comprises:
 switching between a low frequency source and a high frequency source.   
     
     
       42. The method of claim 39, wherein said c) comprises:
 enabling one of a high voltage signal output and a low voltage signal output.   
     
     
       43. The method of claim 39, wherein said c) comprises:
 switching between a low voltage source and a high voltage source.   
     
     
       44. The method of claim 39, wherein said computer system further includes a user input device. 
     
     
       45. The method of claim 39, wherein said computer system further includes a user input device. 
     
     
       46. The method of claim 39, wherein said computer system further includes a power source. 
     
     
       47. A dynamic performance adjustment system comprising:
 a display operable to display information thereon;   a memory device;   a functional circuit for performing operational tasks that have differing minimum frequency and voltage requirements; and   a dynamic performance adjustment control circuit for controlling frequency adjustment and voltage adjustment to said functional circuit, said dynamic performance adjustment control circuit coupled to said functional circuit, wherein said dynamic performance adjustment control circuit:
 a) adjusts frequency and voltage at which said functional circuit operates to a relatively greater frequency and a relatively greater voltage for tasks required to be performed in a shorter duration of time, 
 b) adjusts frequency and voltage at which said functional circuit operates to a relatively lower frequency and a relatively lower voltage for tasks with longer timing tolerance, and 
 c) transmits an operation control signal to said functional circuit directing said functional circuit to cease operations for a period of time sufficient to implement a change to said frequency and said voltage supplied to said functional circuit, said period of time permitting said dynamic performance adjustment control circuit to control frequency adjustment and voltage adjustment to said functional circuit and permitting said dynamic performance adjustment system to stabilize. 
   
     
     
       48. The dynamic performance adjustment system of claim 47, wherein said dynamic performance adjustment control circuit receives a performance indication signal indicating a minimal performance requirement of said functional circuit for a particular one of said operational tasks. 
     
     
       49. The dynamic performance adjustment system of claim 48, wherein said dynamic performance adjustment control circuit controls frequency adjustment and voltage adjustment to said functional circuit in accordance with said performance indication signal. 
     
     
       50. The dynamic performance adjustment system of claim 47, wherein said dynamic performance adjustment control circuit stops a clock signal to said functional circuit and sets a power supply signal to said functional circuit at substantially zero volts when said functional circuit is not actively performing an operation. 
     
     
       51. The dynamic performance adjustment system of claim 47, wherein said functional circuit signals said dynamic performance adjustment control circuit to control frequency adjustment and voltage adjustment for said functional circuit, and wherein said functional circuit ceases operation for a period of time sufficient to permit said dynamic performance adjustment control circuit to control frequency adjustment and voltage adjustment to said functional circuit and permit the dynamic performance adjustment system to stabilize. 
     
     
       52. The dynamic performance adjustment system of claim 47, further comprising a bus. 
     
     
       53. The dynamic performance adjustment system of claim 52, wherein said memory device is coupled to said bus. 
     
     
       54. The dynamic performance adjustment system of claim 53, wherein said dynamic performance adjustment control circuit is coupled to said bus. 
     
     
       55. The dynamic performance adjustment system of claim 47, further comprising an input device. 
     
     
       56. The dynamic performance adjustment system of claim 47, further comprising a communication device for communicating signals. 
     
     
       57. The dynamic performance adjustment system of claim 47, further comprising a power source.