Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter

Abstract

An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of being independently controlled so that data can be written or read in/from the memory banks, each having memory cells arranged in an N×M matrix structure. The memory write/read control unit generates control signals to write/read data in/from the memory unit. The memory access address generation unit generates a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals. The second permutation and output selection unit rearranges the positions of data bits output from the memory unit and outputs the position-rearranged data bits.

What is claimed is: 
     
       1. An interleaving apparatus for an orthogonal frequency division multiplexing transmitter, comprising:
 a memory unit including a plurality of memory banks each having memory cells arranged in an N×M matrix structure, the memory banks being capable of being independently controlled so that data can be written or read in or from the memory banks; 
 a memory write/read control unit for generating controller configured to generate control signals to write/read data in/from the memory unit, according to a constellation mapping scheme related to a data transmission rate , and outputs output the control signals to the memory unit; , and configured to receive signals indicating the data transmission rate and a valid interval of the input data and generate the control signals to write/read data existing in the valid interval;  
 a memory access address generation unit for generating generator configured to generate a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals; and 
 a second permutation and output selection unit for rearranging processor configured to rearrange positions of data bits output from the memory unit and outputting the position-rearranged data bits. 
 
     
     
       2. The interleaving apparatus according to  claim 1 , wherein the memory unit comprises a plurality of 24-bit memory banks. 
     
     
       3. The interleaving apparatus according to  claim 1  or  2 , wherein the memory unit comprises at least 12 memory banks. 
     
     
       4. The interleaving apparatus according to claim 1, wherein each of the memory banks receives or outputs data on a 1-bit-at-a-time basis. 
     
     
       5. The interleaving apparatus according to  claim 1 , wherein each of the memory banks controls write/read operations in response to activation signals of the write/read control signals output from the memory write/read control unit controller. 
     
     
       6. The interleaving apparatus according to  claim 1 , wherein the data input to the memory unit have a 2-bit parallel structure. 
     
     
       7. The interleaving apparatus according to  claim 1 , wherein the memory write/read control unit receives signals indicating the data transmission rate and a valid interval of the input data and generates the control signals to write/read data existing in the valid interval. 
     
     
       8. The interleaving apparatus according to  claim 1 , wherein the memory access address generation unit generator generates an n-bit memory access address, upper k bits of which indicate a column of each memory cell and lower n-k bits of which indicate a row of each memory cell. 
     
     
       9. The interleaving apparatus according to claim 8, wherein n is 5 and k is 2. 
     
     
       10. The interleaving apparatus according to  claim 1 , wherein the second permutation and output selection unit processor comprises:
 a second permutation unit for rearranging processor configured to rearrange the positions of data bits output from the memory unit; and 
 an output selection unit for outputting processor configured to output the position-rearranged data bits and signals indicating a data transmission rate and a valid interval of the output data, and outputting valid data according to the data transmission rate and the valid interval. 
 
     
     
       11. The interleaving apparatus according to  claim 10 , wherein the second permutation unit processor includes 12 bit input ports, which are classified into an inphase block and a quadrature block, each including 6-bit input ports that receive 6-bit parallel data, the 6-bit parallel data corresponding to each block being divided into two 3-bit groups and being input to an odd part and an even part, respectively. 
     
     
       12. The interleaving apparatus according to  claim 10 , wherein the second permutation unit processor outputs 6-bit parallel data, which are classified into an inphase block and a quadrature block, each having 3 bits. 
     
     
       13. The interleaving apparatus according to  claim 10 , wherein the second permutation unit processor selects one of data output corresponding to an odd part and data output corresponding to an even part in response to an odd/even part distinguishing signal generated by the memory write/read control unit controller, and outputs the selected data. 
     
     
       14. The interleaving apparatus according to  claim 10 , wherein the output selection unit processor is operated so that, if a constellation mapping scheme related to a data transmission rate of the output data is BPSK, valid data are output in series on a 1-bit-at-a-time basis, if a constellation mapping scheme is QPSK, valid data are output in parallel on a 2-bits-at-a-time basis, if a constellation mapping scheme is 16-QAM, valid data are output in parallel on a 4-bits-at-a-time basis, and if a constellation mapping scheme is 64-QAM, valid data are output in parallel on a 6-bits-at-a-time basis. 
     
     
       15. An interleaving method for an orthogonal frequency division multiplexing transmitter, the transmitter including a memory write/read control unit controller and a memory access address generation unit generator and writing/reading data in/from a memory unit including a plurality of memory banks each having memory cells arranged in a matrix structure, the memory banks being capable of being independently controlled so that data input from a convolution encoder can be written or read in or from the memory banks, the method comprising the steps of:
 a)generating at the memory write/read control unit generatingcontroller a control signal to write the input data in a corresponding memory bank in response to data transmission rate and valid interval indication signals for the input data transmitted from the convolution encoder; 
 b)generating at the memory access address generation unit generatinggenerator a memory access address to access the memory bank, in which the input data are to be written, in response to the write control signal for the memory bank generated by the memory write/read control unitcontroller; 
 c) writing the input data in a memory bank corresponding to the memory access address in response to the write control signal generated by the memory write/read control unit controller; 
 d)generating at the memory write/read control unit generatingcontroller a control signal to read data, written in the memory bank according to the data transmission rate, and data transmission rate and valid interval indication signals for output data when the data are read from the memory bank; 
 e)generating at the memory access address generation unit generatinggenerator a memory access address to access the memory bank, from which output data are to be read, in response to the read control signal; 
 f) reading the output data from the memory bank in response to the read control signal and the memory access address; 
 g) rearranging positions of output data read from the memory bank; and 
 h) outputting valid data among the position-rearranged output data in response to the data transmission rate and valid interval indication signals for the output data. 
 
     
     
       16. The interleaving method according to  claim 15 , wherein the step a) generating of the control signal to write the input data is performed so that the memory write/read control unit controller generates a control signal to write the input data in 24-bit memory banks. 
     
     
       17. The interleaving method according to  claim 15 , wherein the step a) generating of the control signal to write the input data is performed so that the memory write/read control unit controller generates a control signal to write the input data in at least 12 memory banks. 
     
     
       18. The interleaving method according to claim 15, wherein the data input/output to/from the memory bank are 1-bit data. 
     
     
       19. The interleaving method according to  claim 15 , wherein the data, input to the memory unit, have a 2-bit parallel input structure. 
     
     
       20. The interleaving method according to  claim 15 , wherein the step b) generating of the memory access address is performed to generate the memory access address implemented with an n-bit signal, upper k bits of which indicate a column of each memory cell and lower n-k bits of which indicate a row of each memory cell. 
     
     
       21. The interleaving method according to claim 20, wherein n is 5 and k is 2.  
     
     
       22. The interleaving method according to  claim 15 , wherein the step g) rearranging of the positions of the output data read is performed to output 6-bit parallel data, the 6-bit parallel data being classified into an inphase block and a quadrature block, each having 3 bits. 
     
     
       23. The interleaving method according to  claim 15 , wherein the step g) rearranging of the positions of the output data read is performed so that one of data output corresponding to an odd part and data output corresponding to an even part is selected in response to an odd/even part distinguishing signal generated by the memory write/read control unit, and the selected data are output. 
     
     
       24. The interleaving method according to  claim 15 , wherein the step h) outputting of the valid data is performed so that, if a constellation mapping scheme related to a data transmission rate of the output data is BPSK, valid data are output in series on a 1-bit-at-a-time basis, if a constellation mapping scheme is QPSK, valid data are output in parallel on a 2-bits-at-a-time basis, if a constellation mapping scheme is 16-QAM, valid data are output in parallel on a 4-bits-at-a-time basis, and if a constellation mapping scheme is 64-QAM, valid data are output in parallel on a 6-bits-at a time-basis. 
     
     
       25. The interleaving method according to  claim 15 , wherein the step h) outputting of the valid data comprises the step of outputting the data transmission rate and valid interval indication signals for the output data. 
     
     
       26. An interleaving apparatus for an orthogonal frequency division multiplexing (OFDM) transmitter, the apparatus comprising:
 a memory write/read controller configured to generate a control signal according a constellation mapping scheme related to a data transmission rate, and output the generated control signal, and configured to receive signals indicating the data transmission rate and a valid interval of the input data and generate the control signal to write/read data existing in the valid interval:   a memory configured to store input data and output data bits of the stored data, in response to the control signal outputted from the memory write/read controller; and   a permutation and output selection processor configured to rearrange positions of the data bits outputted from the memory and output the position-rearranged data bits.    
     
     
       27. The apparatus according to claim 26, wherein the memory includes a plurality of memory banks each having memory cells arranged in an N+M matrix structure, the memory banks being independently controlled so that data can be written or read in or from the memory banks.  
     
     
       28. The apparatus according to claim 26, further comprises a memory access address generator configured to generate a memory access address used to write/read data in/from the memory in response to the control signal.  
     
     
       29. An interleaving method for an orthogonal frequency division multiplexing (OFDM) transmitter, the method comprising:
 generating at a memory write/read controller a control signal according to a constellation mapping scheme related to a data transmission rate;   receiving signals indicating the data transmission rate and a valid interval of the input data and generate the control signal to write/read data existing in the valid interval;   storing input data and outputting data bits of the stored data in a memory, in response to the generated control signal;   rearranging positions of the outputted data bits at a permutation and output selection processor; and   outputting the position-rearranged data bits.    
     
     
       30. The method according to claim 29, wherein the method further comprises generating a memory access address used to store the input data and output the data bits of the stored data in response to the control signal.