Method for driving a nonvolatile semiconductor memory device

Abstract

A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode. The method includes to achieve a state in which charges having a first polarity are injected into the floating electrode: providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode.

The invention claimed is: 
     
       1. A method for driving a nonvolatile semiconductor memory device having a semiconductor layer having a channel and source/drain regions provided on both sides of the channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the floating electrode,
 the method comprising, to achieve a state in which charges having a first polarity are injected into the floating electrode: 
 providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; 
 subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and 
 subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode. 
 
     
     
       2. The method according to  claim 1 , wherein
 after providing the third potential difference between the semiconductor and the gate electrode, 
 a fourth potential difference is provided between the semiconductor layer and the gate electrode to inject charges having the second polarity into the second insulating film. 
 
     
     
       3. The method according to  claim 1 , wherein before providing the third potential difference between the semiconductor layer and the gate electrode, defects in a region in the second insulating film near the floating electrode are filled with the charges having the second polarity and defects in a remaining region in the second insulating film are filled with the charges having the first polarity. 
     
     
       4. The method according to  claim 1 , wherein at least any of the first insulating film and the second insulating film includes at least one selected from a group consisting of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate. 
     
     
       5. The method according to  claim 1 , wherein an electric field applied to the first insulating film by the first potential difference and the second potential difference is 20 MV/cm or less. 
     
     
       6. The method according to  claim 1 , wherein an electric field applied to the first insulating film by the first potential difference and the second potential difference is 15 MV/cm or less, and application time of the electric field is 10 seconds or less. 
     
     
       7. The method according to  claim 1 , wherein the providing the first potential difference includes a plurality of providing potential differences to inject the charges having the first polarity into the second insulating film. 
     
     
       8. The method according to  claim 1 , wherein the providing of the second potential difference includes a plurality of providing potential differences to inject the charges having the second polarity into the second insulating film. 
     
     
       9. The method according to  claim 1 , wherein
 the first polarity is negative, 
 the first potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer, 
 the second potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer, and 
 the third potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer. 
 
     
     
       10. The method according to  claim 9 , wherein before providing the third potential difference between the semiconductor layer and the gate electrode, defects in a region in the second insulating film near the floating electrode are filled with holes and defects in a remaining region in the second insulating film are filled with electrons. 
     
     
       11. The method according to  claim 9 , wherein
 after providing the third potential difference between the semiconductor layer and the gate electrode, 
 a fourth potential difference is provided between the semiconductor layer and the gate electrode to inject the charges having the second polarity being positive into the second insulating film. 
 
     
     
       12. The method according to  claim 1 , wherein
 the first polarity is positive, 
 the first potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer, 
 the second potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer, and 
 the third potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer. 
 
     
     
       13. The method according to  claim 12 , wherein before providing the third potential difference between the semiconductor layer and the gate electrode, defects in a region in the second insulating film near the floating electrode are filled with electrons and defects in a remaining region in the second insulating film are filled with holes. 
     
     
       14. The method according to  claim 12 , wherein
 after providing the third potential difference between the semiconductor layer and the gate electrode, 
 a fourth potential difference between the semiconductor layer and the gate electrode to inject the charges having the second polarity being negative into the second insulating film. 
 
     
     
       15. A method for driving a nonvolatile semiconductor memory device having a semiconductor layer having a channel and source/drain regions provided on both sides of the channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the floating electrode,
 the method comprising, to achieve a state in which charges having a first polarity are injected into the floating electrode: 
 providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode; and 
 subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film. 
 
     
     
       16. The method according to  claim 15 , wherein providing the second potential difference between the semiconductor layer and the gate electrode injects the charges having the second polarity into a region of the second insulating film facing the floating electrode. 
     
     
       17. The method according to  claim 15 , wherein at least any of the first insulating film and the second insulating film includes at least one selected from a group consisting of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate. 
     
     
       18. The method according to  claim 15 , wherein
 the first polarity is negative, 
 the first potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer, 
 the second potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer. 
 
     
     
       19. The method according to  claim 15 , wherein
 the first polarity is positive, 
 the first potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer, 
 the second potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer. 
 
     
     
       20. A nonvolatile semiconductor memory device comprising:
 a semiconductor layer having a channel and source/drain regions provided on both sides of the channel; 
 a first insulating film provided on the channel; 
 a floating electrode provided on the first insulating film; 
 a second insulating film provided on the floating electrode; 
 a gate electrode provided on the second insulating film; and 
 a control circuit controlling its data memory state by injection of charges into the floating electrode, 
 the control circuit being configured to perform, to achieve a state in which charges having a first polarity are injected into the floating electrode: 
 providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; 
 subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and 
 subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode. 
 
     
     
       21. A nonvolatile semiconductor memory device comprising:
 a semiconductor layer having a channel and source/drain regions provided on both sides of the channel; 
 a first insulating film provided on the channel; 
 a floating electrode provided on the first insulating film; 
 a second insulating film provided on the floating electrode; 
 a gate electrode provided on the second insulating film; and 
 a control circuit controlling its data memory state by injection of charges into the floating electrode, 
 the control circuit being configured to perform, to achieve a state in which charges having a first polarity are injected into the floating electrode: 
 providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode; and 
 subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film. 
 
     
     
       22. A nonvolatile semiconductor memory device comprising:
 a semiconductor layer;   a first insulating film provided on the semiconductor layer;   an electrode provided on the first insulating film;   a second insulating film having a characteristic to trap charge provided on the electrode side;   a gate electrode provided on the second insulating film; and   a control circuit,   the control circuit being configured to perform a first operation to provide a first potential difference between the gate electrode and the semiconductor layer, to perform a second operation to provide a second potential difference between the gate electrode and the semiconductor layer, and to perform a third operation to provide a third potential difference between the first gate electrode and the semiconductor layer,   the first potential difference having a first polarity,   the second potential difference having a second polarity opposite to the first polarity, and   the third potential difference having the first polarity.   
     
     
       23. The device according to claim 22, wherein the control circuit includes a voltage control circuit, a voltage generation circuit and a read circuit. 
     
     
       24. The device according to claim 22, wherein
 in the first operation, the control circuit is configured to apply a first voltage to the gate electrode and to apply a second voltage lower than the first voltage to the semiconductor layer, and   in the second operation, the control circuit is configured to apply a third voltage to the gate electrode and to apply a fourth voltage higher than the third voltage to the semiconductor layer.   
     
     
       25. The device according to claim 22, further comprising a select transistor provided together with a memory cell and including a select gate, the memory cell including the electrode, the second insulating film and the gate electrode. 
     
     
       26. The device according to claim 25, wherein
 in the first operation, the control circuit is configured to apply a first voltage to the gate electrode and to apply a second voltage lower than the first voltage to the semiconductor layer, and   in the second operation, the control circuit is configured to apply a third voltage to the gate electrode and to apply a fourth voltage higher than the third voltage to the semiconductor layer.   
     
     
       27. The device according to claim 26, wherein in the first operation, the control circuit is configured to apply a fifth voltage to the select gate, and the fifth voltage is lower than the first voltage and higher than the second voltage. 
     
     
       28. The device according to claim 27, wherein in the second operation, the control circuit is configured to turn the select gate off. 
     
     
       29. The device according to claim 22, wherein the electrode includes Si. 
     
     
       30. The device according to claim 29, wherein the second insulating film includes Hf and oxygen. 
     
     
       31. The device according to claim 22, wherein the electrode is based on nanocrystal. 
     
     
       32. The device according to claim 29, wherein the second insulating film includes silicon, nitrogen and oxygen. 
     
     
       33. The device according to claim 29, wherein the electrode has a two- or three-layer structure. 
     
     
       34. The device according to claim 22 wherein the control circuit is configured to perform the second operation after the first operation consecutively. 
     
     
       35. A nonvolatile semiconductor memory device comprising:
 a semiconductor layer;   a first insulating film provided on the semiconductor layer;   an electrode provided on the first insulating film;   a second insulating film having a characteristic to trap charge provided on the electrode side;   a gate electrode provided on the second insulating film; and   a control circuit,   the control circuit being configured to perform a first operation to provide a first potential difference between the gate electrode and the semiconductor layer, and to perform a second operation to provide a second potential difference between the gate electrode and the semiconductor layer,   the first potential difference having a first polarity, and   the second potential difference having a second polarity opposite to the first polarity, wherein   in the first operation, the control circuit is configured to apply a first voltage to the gate electrode and to apply a second voltage lower than the first voltage to the semiconductor layer, and   in the second operation, the control circuit is configured to apply a third voltage to the gate electrode and to apply a fourth voltage higher than the third voltage to the semiconductor layer.   
     
     
       36. The device according to claim 35, wherein the control circuit include a voltage control circuit and a voltage generation circuit and a read circuit. 
     
     
       37. The device according to claim 35, further comprising a select transistor provided together with a memory cell and including a select gate, the memory cell including the electrode, the second insulating film and the gate electrode. 
     
     
       38. The device according to claim 35, wherein in the first operation, the control circuit is configured to apply a third voltage to the select gate, and the third voltage is lower than the first voltage and higher than the second voltage. 
     
     
       39. The device according to claim 38, wherein in the second operation, the control circuit is configured to turn the select gate off. 
     
     
       40. The device according to claim 35, wherein the electrode includes Si. 
     
     
       41. The device according to claim 40, wherein the second insulating film includes Hf and oxygen. 
     
     
       42. The device according to claim 35, wherein the electrode is based on nanocrystal. 
     
     
       43. The device according to claim 40, wherein the second insulating film includes silicon, nitride and oxygen. 
     
     
       44. The device according to claim 40, wherein the electrode has a two- or three-layer structure. 
     
     
       45. The device according to claim 35 wherein the control circuit is configured to perform the second operation after the first operation consecutively. 
     
     
       46. A nonvolatile semiconductor memory device comprising:
 a semiconductor layer;   a first insulating film provided on the semiconductor layer;   an electrode provided on the first insulating film;   a second insulating film having a characteristic to trap charge provided on the electrode side;   a gate electrode provided on the second insulating film; and   a control circuit,   the control circuit being configured to perform a first operation to provide a first potential difference between the gate electrode and the semiconductor layer, to perform a second operation to provide a second potential difference between the gate electrode and the semiconductor layer, and to perform the second operation after the first operation consecutively,   the first potential difference having a first polarity, and   the second potential difference having a second polarity opposite to the first polarity.   
     
     
       47. The device according to claim 46, wherein the control circuit include a voltage control circuit and a voltage generation circuit and a read circuit. 
     
     
       48. The device according to claim 46, further comprising a select transistor provided together with a memory cell and including a select gate, the memory cell including the electrode, the second insulating film and the gate electrode. 
     
     
       49. The device according to claim 46, wherein in the first operation, the control circuit is configured to apply a third voltage to the select gate, and the third voltage is lower than the first voltage and higher than the second voltage. 
     
     
       50. The device according to claim 49, wherein in the second operation, the control circuit is configured to turn the select gate off. 
     
     
       51. The device according to claim 46, wherein the electrode includes Si. 
     
     
       52. The device according to claim 51, wherein the second insulating film includes Hf and oxygen. 
     
     
       53. The device according to claim 46, wherein the electrode is based on nanocrystal. 
     
     
       54. The device according to claim 51, wherein the second insulating film includes silicon, nitride and oxygen. 
     
     
       55. The device according to claim 51, wherein the electrode has a two- or three-layer structure.