Page buffer circuit of memory device and program method

Abstract

A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.

What is claimed is: 
     
       1. A memory device comprising:
 a memory cell array including a plurality of multi-level cells (MLCs) respectively connected to a plurality of bit line pairs and a plurality of word lines; 
 a plurality of page buffer circuits comprising a plurality of latch circuits disposed corresponding to the a plurality of bit line pairs, respectively, wherein each of the page buffer circuits comprises latch circuits and each of the latch circuits outputs a data to be programmed into one of the MLCs connected to a pair bit line of a corresponding bit lines line pair at the time of a program operation, and stores data read from one of the MLCs connected to the pair bit line of the corresponding bit lines line pair, and wherein a first latch circuit included in the plurality of the latch circuits is connected to a data I/O line while a second latch circuit included in the plurality of the latch circuits is not connected to the data I/O line and the second latch circuit stores and outputs an input data received through the first latch circuit; and 
 a plurality of Y gate circuits connected to the plurality of page buffer circuits, respectively, and further connected to the data I/O line, wherein each of the Y gate circuits outputs a program data, which is received through the data I/O line, to the first latch circuit in response to one of I/O control signals at the time of a program operation, and outputs a read data, which is received from the first latch circuit, to the data I/O line at the time of a read operation. 
 
     
     
       2. The memory device of  claim 1 , wherein each of the page buffer circuits comprises:
 a MSB latchwherein the first latch circuit is configured to (i) sense a voltage of a sensing node in response to a first control signal and store an upper sensing data, and output an inverted upper sensing data, or (ii) store an input data and output an inverted input data;, 
 a LSB latchwherein the second latch circuit is configured to (i) sense a voltage of the sensing node in response to thea second control signal, and store and output a lower sensing data, or (ii) store and output an input data received through the MSB latch; first latch circuit, 
 wherein an inverted output circuit is configured to invert data stored in the LSB latch second latch circuit, and output an inverted data to the MSB latch; first latch circuit, and 
 wherein each of the page buffer circuits further comprises a MSB first verification circuit configured to output a first verification signal in response to the data stored in the MSB latch; first latch circuit, and a LSB second verification circuit configured to output a second verification signal in response to the data stored in the LSB latch second latch circuit. 
 
     
     
       3. The memory device of  claim 2 , wherein each of the page buffer circuits further comprises:
 a bit line selection circuit configured to select one of the corresponding bit line pair in response to bit line selection signals and discharge signals, and connect a selected bit line to the sensing node; 
 a precharge circuit configured to internally charge the sensing node in response to a precharge control signal; 
 a data input circuit configured to output the input data, received from a Y gate circuit through a data I/O node, to the MSB first latch circuit in response to data input signals; and 
 a data output circuit configured to output the data of the MSB first latch circuit to a Y gate according to the a third control signal. 
 
     
     
       4. The memory device of  claim 2 , wherein the MSB first latch circuit comprises:
 a MSB sensing circuit configured to generate a MSB data according to the voltage of the sensing node; 
 a MSB latch circuit configured to latch the MSB data and output an inverted MSB data, or latch a LSB data received from the a data input circuit, and output an inverted LSB data to the LSB second latch circuit; and 
 an inverted data output circuit configured to invert the MSB or LSB data stored in the MSB latch circuit, and output an inverted data; and 
 a data transmission circuit configured to transfer data, received from the data input circuit, to the MSB latch circuit. 
 
     
     
       5. The memory device of  claim 2 , wherein the LSB second latch circuit comprises:
 a LSB sensing circuit configured to generate a LSB data according to the voltage of the sensing node; 
 a LSB latch circuit configured to latch the LSB data and output a latched LSB data; and 
 a LSB output circuit configured to output data, stored in the LSB latch circuit, to the sensing line node. 
 
     
     
       6. A memory device comprising:
 a memory cell array including multi-level cells (MLCs);   page buffer circuits coupled to the memory cell array through bit lines, the page buffer circuits including a first page buffer circuit that includes first and second latch circuits coupled to a corresponding bit line, wherein the first latch circuit is connected to a data line while the second latch circuit is not connected to the data line; and   Y gate circuits, including a first Y gate circuit coupled to the first page buffer circuit and the data line, the first Y gate circuit being configured to transfer program data from the data line to the first page buffer circuit in a program operation and being configured to transfer read data received from the first page buffer circuit to the data line in a read operation, and   wherein the second latch circuit is configured to store and output an input data received through the first latch circuit.   
     
     
       7. The memory device of claim 6, wherein the program data is most significant bit (MSB) data. 
     
     
       8. The memory device of claim 7, wherein the first latch circuit is configured to receive and store the MSB data from the data line through the first Y gate circuit,
 wherein the first latch circuit is further configured to perform a first verification to determine whether a multi-level cell coupled to the corresponding bit line has a first logic state, and   wherein the first latch circuit is further configured to transfer the MSB data to the second latch circuit for storage prior to the first verification.   
     
     
       9. The memory device of claim 8, wherein the first latch circuit is configured to receive and store sensing data through a corresponding bit line during the first verification. 
     
     
       10. The memory device of claim 9, wherein after the first verification, the second latch circuit is configured to transfer the stored MSB data to the first latch circuit,
 wherein the second latch circuit is further configured to perform a second verification to determine whether the multi-level cell coupled to the corresponding bit line has a second logic state, and   wherein the first latch circuit is configured to store the MSB data prior to the second verification.   
     
     
       11. The memory device of claim 10, wherein the second latch circuit is configured to receive and store another sensing data through the corresponding bit line during the second verification. 
     
     
       12. The memory device of claim 11, wherein the first latch circuit is configured to program the stored MSB data into the multi-level cell coupled to the corresponding bit line based on results of the first verification and the second verification. 
     
     
       13. The memory device of claim 6, wherein the program data is least significant bit (LSB) data. 
     
     
       14. The memory device of claim 13, wherein the second latch circuit is configured to program the stored LSB data into a multi-level cell through a corresponding bit line. 
     
     
       15. The memory device of claim 6, wherein the second latch circuit is configured to transfer the read data through the first latch circuit to the first Y gate circuit. 
     
     
       16. The memory device of claim 6, wherein each of the page buffer circuits includes first and second latch circuits coupled to a corresponding bit line, and wherein each of the Y gate circuits is coupled to a corresponding first page buffer circuit and a corresponding data line.