High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory

Abstract

An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

We claim: 
     
       1. A method of improving performance for a computer processor, said method comprising:
 receiving in an input/output processor data and a memory access instruction from said computer processor, said memory access instruction identifying a type of memory storage task from a group of more than one different memory storage task; 
 analyzing said memory access instruction in said input/output processor to identify said type of memory storage task; 
 if said type of memory storage task comprises a counter adjustment then
 updating a value containing recent adjustments to said counter in a higher-speed memory, and 
 updating a full version of said counter in a slower-speed memory if an overflow of said value containing recent adjustments to said counter occurs; and 
 
 if said type of memory storage task comprises a write to a FIFO queue then
 storing said data in a queue tail of said FIFO queue in said higher-speed memory, and 
 moving data from said queue tail to a queue body of said FIFO queue in said slower-speed memory if said queue tail is filled 
 
 receiving in an input/output processor, data and multiple memory access instructions from said computer processor; 
 said received multiple memory access instructions indicating memory access type pattern from a group of more than one different memory access type patterns that includes a first memory access type pattern and a second memory access type pattern; 
 analyzing said received multiple memory access instructions in said input/output processor to identify said memory access type pattern; 
 using the input/output processor to perform a first high frequency memory write task and a first low frequency memory write task in response to identification of the first memory access type pattern, wherein data written using the first low frequency memory write task is accessed less frequently than data written using the first high frequency memory write task; 
 using the input/output processor to perform a second high frequency memory write task and a second low frequency memory write task in response to identification of the second memory access type pattern, wherein data written using the second low frequency memory write task is accessed less frequently than the second high frequency memory write task; 
 if the memory access type pattern is the first memory access type pattern,
 performing the first high frequency memory write task in a higher-speed memory; and 
 performing the first low frequency memory write task in a slower-speed memory; and 
 
 if the memory access type pattern is the second memory access type pattern,
 performing the second high frequency memory write task in the higher-speed memory; and 
 performing the second low frequency memory write task in the slower-speed memory. 
 
 
     
     
       2. The method as claimed in  claim 1  wherein said higher-speed memory comprises static random access memory (SRAM). 
     
     
       3. The method as claimed in  claim 1  wherein said slower-speed memory comprises dynamic random access memory (DRAM). 
     
     
       4. The method as claimed in  claim 1  wherein said a FIFO queue further comprises a tail of said FIFO queue in said higher-speed memory. 
     
     
       5. The method as claimed in  claim 1 , said method further comprising:
 if said type of memory storage task comprises a counter read then
 generating a sum by adding said value containing recent adjustments to said counter to said full version of said counter in said slower speed memory, and returning said sum. 
   
     
     
       6. The method as claimed in  claim 1 , said method further comprising:
 if said type of memory storage task comprises a read from said FIFO queue then
 responding with data from in a queue head of said FIFO queue in said higher-speed memory, and 
 moving data from said queue body of said FIFO queue in said slower-speed memory to said queue head in said higher-speed memory. 
   
     
     
       7. The method of claim 1 including not performing the first low frequency memory write task unless required to keep the first higher-speed memory available during the memory task. 
     
     
       8. The method of claim 1 wherein the second memory write task is an adjustment to a counter,
 wherein performing the second high frequency memory write task is storing an adjustment value in the higher-speed memory, and   wherein performing the second low frequency memory write task is storing a counter value in the slower-speed memory.   
     
     
       9. The method of claim 8, wherein the counter is updated to the slower-speed memory when there is an overflow of the adjustment value. 
     
     
       10. The method of claim 8, wherein the counter is updated to the slower-speed memory when there is an overflow of the adjustment value during the memory task. 
     
     
       11. The method of claim 1, wherein the first memory write task is to write to a First In First Out (FIFO) queue,
 wherein performing the first high frequency memory write task is storing data in a queue tail of the FIFO queue in the higher-speed memory, and   wherein performing the first low frequency write memory task is storing data in a queue body of the FIFO queue in the slower-speed memory.   
     
     
       12. The method of claim 11, performing the first low frequency memory write task when required to keep the memory allocated for the FIFO queue in the higher-speed memory available. 
     
     
       13. The method of claim 11, including performing the first low frequency memory task when required to keep the memory allocated for the FIFO queue in the higher-speed memory available. 
     
     
       14. The method of claim 1, wherein the second memory write task is to read a counter,
 wherein performing the second high frequency memory write task is updating an adjustment value in the higher-speed memory, and   wherein performing the second low frequency memory write task is storing the counter value in the slower-speed memory.   
     
     
       15. The method of claim 14 including performing the second low frequency memory write task of storing the counter value in the slower-speed memory when an overflow of adjustment values occurs. 
     
     
       16. The method of claim 1, wherein the first memory task is to read a First In First Out (FIFO) queue,
 wherein performing the first high frequency memory write task is reading a queue head, and   wherein performing the first low frequency memory write task is reading the queue body of the FIFO queue.   
     
     
       17. The method of claim 1, wherein the first memory write task is read-modify-write of a state data,
 wherein performing the first low frequency memory write task is storing the state data in a different location for a consecutive update, and   wherein the consecutive updates are in different memory banks in the slower-speed memory.   
     
     
       18. The method of claim 1, wherein the second memory write task is an adjustment to a value,
 wherein performing the second high frequency memory write task is updating the adjustment of the value in the higher-speed memory.   
     
     
       19. The method of claim 18, wherein performing the second low frequency memory write task is updating to slower-speed memory the value when there is an overflow of the adjustment value in the higher-speed memory. 
     
     
       20. The method of claim 1,
 wherein at least one memory write task includes multiple memory accesses in response to a single memory access instruction.   
     
     
       21. A method of improving performance for a computer processor, said method comprising:
 receiving in an input/output processor data and a memory access instruction from said computer processor;   said memory access instruction identifying a type of memory task from a group of more than one different memory task;   analyzing said memory access instruction in said input/output processor to identify said type of memory task;   dividing the memory task into a first memory task and a second memory task;   performing the first memory task in a higher-speed memory to provide access to low latency data;   performing the second memory task in a slower-speed memory to provide access to high latency data;   if said type of memory storage task comprises a counter adjustment then updating a value containing recent adjustments to said counter in a higher-speed memory, and updating a full version of said counter in a slower-speed memory if an overflow of said value containing recent adjustments to said counter occurs; and   if said type of memory storage task comprises a write to a FIFO queue then storing said data in a queue tail of said FIFO queue in said higher-speed memory, and moving data from said queue tail to a queue body of said FIFO queue in said slower-speed memory if said queue tail is filled.