Writing system and method for phase change memory

Abstract

An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

What is claimed is: 
     
       1. A writing system for a phase change memory, comprising:
 a first phase change memory (PCM) cell and a second PCM cell; 
 a first writing circuit, executing a writing procedure, receiving and writing a first data to the first PCM cell; and 
 a verifying circuit executing a verifying procedure, wherein the verifying circuit further comprises,
 a processing unit reading and comparing the data stored in the second PCM cell with a second data, and 
 a second writing circuit to write the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched. 
 
 
     
     
       2. The system as claimed in  claim 1 , the processing further comprising:
 a reading circuit to read the data stored in the second PCM cell; and 
 a processor to compare the second data with the data stored in the second PCM cell and output a current adjustment signal to the first writing circuit and the second writing circuit based on the comparison result. 
 
     
     
       3. The system as claimed in  claim 2 , further comprising:
 a first transistor having a first control terminal, a first input terminal and a first output terminal, wherein the first output terminal is coupled to the first PCM cell and the first control terminal is controlled by a first control signal; and 
 a second transistor having a second control terminal, a second input terminal and a second output terminal, wherein the second input terminal is coupled to the reading circuit, the second output terminal is coupled to the second PCM cell and the second control terminal is controlled by a second control signal. 
 
     
     
       4. The system as claimed in  claim 3 , wherein the W/L width-to-length (W/L) ratio of the second transistor is smaller than the W/L ration of the first transistor. 
     
     
       5. The system as claimed in  claim 2 , wherein the processor further comprises:
 a detection and comparison circuit to compare the data stored in the second PCM cell with a second data to output a comparison signal; and 
 a current adjustment control circuit receiving the comparison signal to output the current adjustment signal. 
 
     
     
       6. The system as claimed in  claim 2 , wherein the first writing circuit further comprises a first auxiliary writing circuit receiving the current adjustment signal to adjust the magnitude of the writing current output by the first writing circuit. 
     
     
       7. The system as claimed in  claim 6 , wherein the first auxiliary writing circuit comprises a current mirror circuit generating an auxiliary current based on a reference current and outputting the auxiliary current to the first writing circuit based on the current adjustment signal. 
     
     
       8. The system as claimed in  claim 2 , wherein the second writing circuit further comprises a second auxiliary writing circuit receiving the current adjustment signal to adjust the magnitude of the writing current output by the second writing circuit. 
     
     
       9. The system as claimed in  claim 8 , wherein the second auxiliary writing circuit comprises a current mirror circuit generating an auxiliary current based on a reference current and outputting the auxiliary current to the second writing circuit based on the current adjustment signal. 
     
     
       10. The system as claimed in  claim 1 , wherein the writing procedure and the verifying procedure are executed in the same cycle. 
     
     
       11. A writing method for a phase change memory, implemented by a first writing circuit and a verifying circuit, wherein the method comprises:
 performing a writing procedure to a first phase change memory (PCM) cell in a first cycle; 
 performing a verifying procedure to a second PCM cell in the first cycle; and 
 if the verifying result of the second PCM cell is not matched, the verifying circuit outputs a current adjustment signal to the first writing circuit to adjust a first writing current output by the first writing circuit. 
 
     
     
       12. The method as claimed in  claim 11 , wherein if the writing procedure is not finished and the first writing circuit receives the current adjustment signal, the first writing circuit adjusts the first writing current based on the current adjustment signal and re-executes the writing procedure to the first PCM cell. 
     
     
       13. The method as claimed in  claim 11 , wherein the verifying circuit further comprises a second writing circuit and when the verifying result of the second PCM cell is wrong, the second writing circuit receives the current adjustment signal to adjust a second writing current output by the second writing circuit and re-executes the writing procedure to the second PCM cell. 
     
     
       14. The method as claimed in  claim 11 , further comprising:
 performing the writing procedure to a third PCM cell in a second cycle; and 
 performing the verifying procedure to the first PCM cell in the second cycle. 
 
     
     
       15. The method as claimed in  claim 11 , wherein the verifying procedure further comprises:
 reading the data stored in the second PCM cell; 
 comparing the data stored in the second PCM cell with a reference data; and 
 if the data stored in the second PCM cell and the reference data are not matched, a current adjustment control signal is input to the first writing circuit. 
 
     
     
       16. The method as claimed in  claim 15 , wherein the verifying procedure further comprises:
 if the data stored in the second PCM cell and the reference data are matched, a verify signal is transmitted to the first writing circuit to maintain the magnitude of the first writing current. 
 
     
     
       17. A method, comprising:
 writing data to a non-volatile memory;   comparing the written data with reference data, wherein said comparing the written data with reference data comprises comparing a resistance of the non-volatile memory with a reference resistance;   determining that the written data does not match the reference data; and   in response to said determining that the written data does not match the reference data, writing the reference data to the non-volatile memory.    
     
     
       18. The method of claim 17, wherein said determining that the written data does not match the reference data comprises determining that the resistance of the non-volatile memory is different from the reference resistance.  
     
     
       19. The method of claim 18, wherein the resistance of the non-volatile memory is less than the reference resistance.  
     
     
       20. The method of claim 17, wherein the reference resistance is associated with a memory reset operation.  
     
     
       21. The method of claim 17, wherein the reference resistance is associated with a memory set operation.  
     
     
       22. The method of claim 17, further comprising adjusting a writing current, wherein the reference data is written to the non-volatile memory using the adjusted writing current.  
     
     
       23. A method, comprising:
 writing, with a first writing circuit, data to a non-volatile memory;   comparing the written data with reference data;   determining that the written data does not match the reference data; and   in response to said determining that the written data does not match the reference data, writing, with a second writing circuit, the reference data to the non-volatile memory.    
     
     
       24. The method of claim 23, wherein the data is written to a first memory location of the non-volatile memory, and wherein the reference data is written to a second location of the non-volatile memory.  
     
     
       25. The method of claim 23, further comprising generating a current adjustment signal, wherein the second writing circuit writes the reference data using the current adjustment signal.  
     
     
       26. The method of claim 25, further comprising writing, with the first writing circuit, other data to a third memory location of the non-volatile memory using the current adjustment signal.  
     
     
       27. The method of claim 26, wherein the written data is compared with the reference data while the first writing circuit writes the other data.  
     
     
       28. A system, comprising:
 a writing circuit configured to write data to a non-volatile memory, wherein the data is written to a first location of the non-volatile memory;   a reading circuit configured to read a resistance from the non-volatile memory; and   a current adjustment circuit configured to output a current adjustment signal if the resistance does not match reference data, wherein the writing circuit is further configured to write another data to a second location of the non-volatile memory using the current adjustment signal.    
     
     
       29. The system of claim 28, wherein the reading circuit comprises a first transistor having a different width-to-length (W/L) ratio than a second transistor associated with the writing circuit.  
     
     
       30. The system of claim 29, wherein the first transistor has a smaller W/L ratio than the second transistor.  
     
     
       31. The system of claim 28, wherein the writing circuit is further configured to re-write the reference data to the non-volatile memory using the current adjustment signal.  
     
     
       32. A system, comprising:
 a writing circuit configured to write data to a non-volatile memory, wherein the data is written to a first location of the non-volatile memory;   a reading circuit configured to read a resistance from the non-volatile memory;   a current adjustment circuit configured to output a current adjustment signal if the resistance does not match reference data; and   another writing circuit configured to re-write the reference data to a second location of the non-volatile memory using the current adjustment signal.    
     
     
       33. The system of claim 32, further comprising a processing unit configured to determine that the resistance does not match the reference data, wherein the other writing circuit is configured to re-write the reference data to the second location of the non-volatile memory in response to a determination that the resistance does not match the reference data.  
     
     
       34. The system of claim 32, further comprising a processing unit configured to determine that the resistance is less than the reference data, wherein the other writing circuit is configured to re-write the reference data to the second location of the non-volatile memory in response to a determination that the resistance is less than the reference data.