Programmable signal routing systems having low static leakage

Abstract

Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus parasitic current sinking or current sourcing leakage paths through the bus-accessing multiplexers are cut off. The method is of particular utility in a low power FPGA that desirable has low static current leakage when in a static state.

What is claimed is: 
     
       1. A programmable logic device (PLD) having a configurable interconnect structure including longline buses each having a plurality of longlines that each extends through a plurality of substantially repeating tile structures of the PLD, where the configurable interconnect structure is characterized by:
 (a) each of the longlines having plural tristate drivers connected thereto and operable to drive that longline; 
 (b) each of the longline-driving tristate drivers having an input terminal, an output enabling terminal and an output terminal that is connected to the corresponding longline of that tristate driver; 
 (c) each of the longline-driving tristate drivers having a corresponding input signal selecting multiplexer coupled to the input terminal of that tristate driver, the input signal selecting multiplexer being operable to supply a selected one of one or more input signals received by the input signal selecting multiplexer, if any are received, to the corresponding input terminal of the tristate driver; 
 (d) each input signal selecting multiplexer being responsive to a respective input selecting signal that is conveyable to that input signal selecting multiplexer, where the input selecting signal can represent 2 n  unique selection states, where n is a whole number greater than 1; 
 (e) each input signal selecting multiplexer of a respective tristate driver having a plurality of, but no more than 2 n −1 usable input terminals to which respective input signals can be supplied for selective routing thereof through the input signal selecting multiplexer to the input terminal of the corresponding tristate driver in accordance with the respective input selecting signal of that input signal selecting multiplexer; 
 (f) each input signal selecting multiplexer being structured such that a predetermined one of the 2 n  unique selection states is a no-usable-input-selected state wherein none of the no more than 2 n −1 usable input terminals of that multiplexer is selected; and 
 (g) the output enabling terminal of each longline-driving tristate driver is controlled by a respective output enabling circuit that is responsive to the respective input selecting signal of the corresponding input signal selecting multiplexer of that tristate driver, where the respective output enabling circuit is structured to prevent the corresponding tristate driver from being in a signal outputting state other than a high impedance (Hi-Z) output state when respective input selecting signal represents said no-usable-input-selected state. 
 
     
     
       2. The PLD of  claim 1  where said configurable interconnect structure is further characterized by:
 said no-usable-input-selected state being defined by the input selecting signal digitally representing an all bits being zeroed state; 
 the PLD has a plurality of configuration memory cells which are globally resettable to an every configuration memory cell being zeroed state; and 
 at least a subset of the configuration memory cells are operatively coupled to the input signal selecting multiplexers of the longline tristate drivers of the PLD so as to define the respective input selecting signals of those input signal selecting multiplexers. 
 
     
     
       3. The PLD of  claim 1  where said respective output enabling circuits of the respective tristate drivers are each operatively coupled so as to be globally driven by a global output enable signal and are each structured to responsively force their corresponding tristate driver into a globally forced Hi-Z output state when the global output enable signal is de-asserted. 
     
     
       4. The PLD of  claim 1  where said configurable interconnect structure is further characterized by:
 the up to 2 n −1 usable input terminals of each input signal selecting multiplexer within a subset of the input signal selecting multiplexers being respectively connected to a corresponding number of adjacent and locally tappable longlines of an adjacent longlines bus, whereby the input signal selecting multiplexer of said subset is defined as a longlines bus accessing multiplexer. 
 
     
     
       5. The PLD of  claim 4  where each of the longlines buses that is accessed by one or more of said longlines bus accessing multiplexers consists of 2 n −1 longlines. 
     
     
       6. The PLD of  claim 4  where the longlines are each a 12-span longline or longer that spans from a first end tile to a corresponding 12 or more further tile structures of the PLD. 
     
     
       7. The PLD of  claim 1  where the PLD includes a field programmable gate array (FPGA). 
     
     
       8. The PLD of  claim 1  wherein:
 each of the longline-driving tristate drivers has a complementary output structure coupled to the output terminal of the tristate driver, the complementary output structure including a current sourcing transistor and a current sinking transistor; and 
 each of the longline-driving tristate drivers has output disabling logic configured to disable each of the current sourcing transistor and the current sinking transistor from conducting current in response to the output enabling terminal of the tristate driver not receiving and output enabling signal from said respective output enabling circuit of the tristate driver. 
 
     
     
       9. The PLD of  claim 8  wherein:
 output disabling logic of each longline-driving tristate driver includes AND gate logic and NAND gate logic coupled one to the next, the AND gate logic and the NAND gate logic also being coupled to drive the current sinking transistor and the current sourcing transistor of the tristate driver; 
 a first of the AND gate and the NAND gate logics being responsive to a data signal supplied to the input terminal of the tristate driver; and 
 a second of the AND gate and the NAND gate logics being responsive both to the respective output enabling circuit of the tristate driver and to a global output enabling signal of a global OE line of the PLD. 
 
     
     
       10. The PLD of  claim 8  wherein:
 the PLD includes a global OE line operatively coupled to supply a corresponding global output enabling signal; and 
 said output disabling logic of each longline-driving tristate driver is configured to additionally disable each of the current sourcing transistor and the current sinking transistor of the tristate driver from conducting current in response to the global OE line not supplying a corresponding global output enabling signal to the output disabling logic. 
 
     
     
       11. The PLD of  claim 10  wherein:
 said output disabling logic of each longline-driving tristate driver is configured to additionally disable each of the current sourcing transistor and the current sinking transistor of the tristate driver from conducting current in response to a dynamic output enabling signal not being provided in an asserting form (an output enabling form) to the output disabling logic. 
 
     
     
       12. The PLD of  claim 1  wherein each input signal selecting multiplexer has:
 a plurality of switchable resistance elements coupled substantially in the form of a binary tree between the no more than 2 n −1 usable input terminals of the multiplexer and a selection outputting terminal of the multiplexer, where the switchable resistance elements are each switchable between a relatively low resistance mode (Low-R) and a substantially higher resistance mode (High-R); and 
 a resistance elements controlling circuit coupled to the switchable resistance elements and configured to form a relatively low resistance pathway between a selected one of the no more than 2 n −1 usable input terminals of the multiplexer and the selection outputting terminal when the respective input selecting signal of the multiplexer indicates selection of the selected one of the no more than 2 n −1 usable input terminals,
 where the resistance elements controlling circuit is further configured to not form a relatively low resistance pathway between any of the no more than 2 n −1 usable input terminals of the multiplexer and the selection outputting terminal when the respective input selecting signal represents the no-usable-input-selected state. 
 
 
     
     
       13. The PLD of  claim 12  wherein each switchable resistance element includes a transmission gate. 
     
     
       14. The PLD of  claim 12  wherein each switchable resistance element includes a pass transistor. 
     
     
       15. The PLD of  claim 12  wherein:
 each given one of the no more than 2 n −1 usable input terminals of the respective multiplexer is coupled in series to a corresponding, first column switchable resistance element such that causing that corresponding first column switchable resistance element of the given usable input terminal to be in the higher resistance mode (High-R) forces leakage current (I Leak ) flowing between the given usable input terminal and any others of the no more than 2 n −1 usable input terminals to flow through the corresponding first column switchable resistance element of the given usable input terminal; and 
 the resistance elements controlling circuit is further configured to respond to the no-usable-input-selected state by causing all the first column switchable resistance elements of the respective multiplexer to be in the higher resistance mode (High-R). 
 
     
     
       16. The PLD of  claim 1  and further comprising a plurality of configuration memory cells,
 wherein each input signal selecting multiplexer receives its respective input selecting signal from a corresponding subset of the configuration memory cells; 
 each configuration memory cell includes a nonvolatile memory part and a corresponding volatile memory part, where the volatile memory part can be programmed with data transferred thereto from the nonvolatile memory part; and 
 where the volatile memory part is responsive to a global control signal of the PLD that, when asserted, places all volatile memory parts in respective states corresponding to the no-usable-input-selected state. 
 
     
     
       17. The PLD of  claim 16  wherein the no-usable-input-selected state is represented by an all zeroed digital signal and the global control signal is a global reset signal that, when asserted, places all the volatile memory parts of the PLD each into a zeroed state. 
     
     
       18. The PLD of  claim 1  wherein:
 at least one of the corresponding input signal selecting multiplexers of a given first longline-driving tristate driver that is connected to drive a respective longline in a corresponding first longlines bus is also connected to function as a longlines accessing multiplexer for one or more longlines of a second longlines bus, where said longlines accessing function includes accessing a signal of an accessed longline in the second longlines bus for potential selective routing of that accessed signal to first longline-driving tristate driver. 
 
     
     
       19. The PLD of  claim 1  wherein said configurable interconnect structure is further characterized by:
 each of said plurality of longlines belongs to a corresponding longlines bus that has at least 2 n′ −1 such longlines extending through the PLD, where n′ is a whole number greater than 1; and 
 each given longlines bus has a plurality of bus-accessing multiplexers operatively coupled thereto, each of the bus-accessing multiplexers being configured to selectively access a selectable signal from a corresponding 2 n′ −1 locally tappable longlines of the given longlines bus,
 where each bus-accessing multiplexer of the given longlines bus is controlled by a corresponding access selection defining signal that can represent 2 n′  unique states, but the respective bus-accessing multiplexer has no more than 2 n′ −1 usable bus-accessing input terminals, and where each bus-accessing multiplexer is structured such that a predetermined one of the 2 n′  unique selection states of the access selection defining signal is a no-usable-access-point selected state wherein none of the no more than 2 n′ −1 usable bus-accessing input terminals of that bus-accessing multiplexer is selected; and 
 where n′ can be equal to n and one or more of the tristate input signal selecting multiplexers can also serve as a bus-accessing multiplexer for a different longlines bus than the longlines bus whose longline is drivable by the corresponding tristate driver of the multiplexer that serves both as a tristate input signal selecting multiplexer and as a bus-accessing multiplexer. 
 
 
     
     
       20. The PLD of  claim 19  where the condition of the access selection defining signal representing the predetermined no-usable-access-point selected state causes the corresponding bus-accessing multiplexer to present a relatively high resistance (Hi-R) at each of its no more than 2 n′ −1 usable bus-accessing input terminals. 
     
     
       21. The PLD of  claim 19  where those of the input signal selecting multiplexers that do not also serve as bus-accessing multiplexers also present a relatively high resistance (Hi-R) at each of their no more than 2 n −1 usable input terminals when the predetermined no-usable-input selected state is indicated by their respective input selecting signals. 
     
     
       22. The PLD of  claim 19  where there is at least one bus-accessing multiplexer in each of the tiles spanned by at least one of the given longlines buses. 
     
     
       23. The PLD of  claim 19  and further comprising:
 a plurality of general purpose interconnect multiplexers (G-Muxes) each having a respective number of 2 m  usable input terminals where m is a whole number greater than 1, where the G-Muxes are responsive to selection control signals supplied thereto and indicating, which, if any, of their 2 m  usable input terminals is to operate as a selected input terminal whose signal is to be operatively coupled to an output terminal of the respective G-Mux, and where the G-Muxes are further each responsive to a corresponding input-and-output enabling configuration signal, which when de-asserted causes the 2 m  usable input terminals and the output terminal of the respective G-Mux to switch into a relatively high resistance mode (Hi-R) whereby possibility of substantial leakage currents flowing between the 2 m  usable input terminals of the so-disabled G-Mux is substantially reduced and possibility of the 2 m  usable input terminals of the so-disabled G-Mux capacitively loading nodes to which they are connected is substantially reduced. 
 
     
     
       24. The PLD of  claim 23  wherein the input-and-output enabling configuration signal of each G-Mux is automatically de-asserted by a global reset signal applied to the configuration memory of the PLD. 
     
     
       25. The PLD of  claim 23  wherein the G-Muxes are disposed in repeated tile structures of the PLD and at least one input terminal of each given G-Mux connects to a tap node within a tile structure other than the tile structure of the given G-Mux. 
     
     
       26. A programmable logic device (PLD) formed as part of a monolithically integrated circuit and comprising:
 a first plurality of input selective first components each having a respective plurality of first input terminals and a respective input selecting capability whereby the first component can select a subset from among a set of input signals received by its respective plurality of first input terminals; 
 a second plurality of selection signal conveying lines that are operatively coupled to convey corresponding first input selecting signals to corresponding ones of the input selective first components, where each of the first components is configured to select its respective subset of input signals in accordance with the first input selecting signal conveyed thereto, where each of the first input selecting signals represents a respective plurality of bits that, when they are all used within the PLD, are capable of defining 2 n  unique states, where n is a whole number greater than 1; and 
 a global selection establishing circuit that is structured to be selectively activated, and when activated, to cause all the first input selecting signals to represent a predetermined one among the 2 n  unique states; 
 wherein each of the input selective first components has no more than 2 n −1 usable input terminals as its respective plurality of first input terminals, and 
 wherein each of the input selective first components automatically responds to the predetermined one of the 2 n  unique states being represented by its first input selecting signal, by switching into a no-usable-input-selected state wherein the input selective first component does not use any of the up to 2 n −1 input signals that may be present on its no more than 2 n −1 usable input terminals. 
 
     
     
       27. The PLD of  claim 26  and further comprising:
 a plurality of multi-line buses each having a respective plurality of lines; 
 wherein the first plurality of input selective first components includes a plurality of bus-accessing multiplexers each having at least a subset of its no more than 2 n −1 usable input terminals connected to a corresponding bus line of a corresponding one of the multi line buses; 
 wherein when each of the bus-accessing multiplexers switches to its no-usable-input-selected state, it presents a relatively high impedance at each of its no more than 2 n −1 usable input terminals so as to thereby substantially not capacitively load the bus lines to which it is connected when it is in the no-usable-input-selected state; and 
 wherein when each of the bus-accessing multiplexers is instead in a usable-input-selected state for which at least one of its usable input terminals is selected, the bus-accessing multiplexer presents a substantially lower impedance at its selected at least one usable input terminal where the lower impedance effectively couples a capacitive load of an opposed end thereof to the selected usable input terminal. 
 
     
     
       28. The PLD of  claim 26  and further comprising:
 an interconnect structure including a plurality of multi-line tristate buses each having a respective plurality of tristate lines, the interconnect structure having plural signal extraction nodes from which signals conveyed by the interconnect structure can be extracted and the interconnect structure having plural signal injection nodes into which signals can be injected for conveyance by the interconnect structure; 
 a plurality of tristate bus drivers each having a tristateable output connected to a signal injection node of a corresponding tristate line; 
 wherein the first plurality of input selective first components includes a plurality of tristate-bus-driver input selecting multiplexers each having an output thereof coupled to an input of a corresponding one of the tristate-bus-drivers, 
 wherein each of the input selecting multiplexers has at least a subset of its no more than 2 n −1 usable input terminals connected to different signal extraction nodes of the interconnect structure; 
 wherein when each of the input selecting multiplexers switches to its no-usable-input-selected state, it presents a relatively high impedance at its each of its no more than 2 n −1 usable input terminals so as to thereby substantially not capacitively load the signal extraction nodes of the interconnect structure to which it is connected when it is in the no-usable-input-selected state; and 
 wherein when each of the input selecting multiplexers is instead in a usable-input-selected state for which at least one of its usable input terminals is selected, the bus-accessing multiplexer presents a substantially lower impedance at its selected at least one usable input terminal where the lower impedance can then effectively couple a capacitive load of an opposed end thereof to the selected usable input terminal. 
 
     
     
       29. The PLD of  claim 28  wherein:
 each tristate bus driver that has a corresponding one of the input selecting multiplexers coupled to the tristate bus driver for driving the tristate bus driver, also has a corresponding output enabling circuit that is responsive to the first input selecting signal of the corresponding input selecting multiplexer and that is structured to switch the output of the tristate bus driver between a driving mode and a high impedance (Hi-Z) mode; 
 wherein the corresponding output enabling circuit of each tristate bus driver with a corresponding input selecting multiplexer is configured to switch the output of the tristate bus driver to the Hi-Z mode when the first input selecting signal of the corresponding input selecting multiplexer indicates the no-usable-input-selected state. 
 
     
     
       30. The PLD of  claim 29  wherein:
 the PLD includes a global disabling circuit configured to selectively output a global output disable signal indicating that the outputs of all the tristate bus drivers of the PLD should be switched into their respective Hi-Z modes; and 
 wherein the corresponding output enabling circuit of each tristate bus driver with a corresponding input selecting multiplexer is further configured to switch the output of the tristate bus driver to the Hi-Z mode when the global output disable signal is asserted. 
 
     
     
       31. The PLD of  claim 30  wherein:
 the PLD includes a programmable configuration memory having plural memory cells, each memory cell having a configuration data outputting part and a reprogrammable configuration data storing part coupled to supply stored configuration data to its respective configuration data outputting part; 
 the PLD includes a global configuration state establishing circuit configured to selectively output a global configuration data establishing signal indicating that the configuration data outputting parts of all the configuration memory cells should be switched into states representing the no-usable-input-selected state; and 
 the configuration data outputting parts of the programmable configuration memory are configured to respond to assertion of the global configuration data establishing signal by outputting configuration data representing the no-usable-input-selected state; 
 wherein the input selecting multiplexers receive their respective first input selecting signals from corresponding ones of the configuration data outputting parts that output configuration data representing the no-usable-input-selected state when the global configuration data establishing signal is asserted. 
 
     
     
       32. The PLD of  claim 31  wherein:
 the PLD includes a configuration bits programming circuit that is configured to sequentially supply configuration data to selectable subsets of the reprogrammable configuration data storing parts of the PLD; 
 wherein the PLD configuration bits programming circuit is configured to automatically cause the global configuration state establishing circuit to temporarily assert the global configuration data establishing signal before new configuration data is programmed into selected subsets of the reprogrammable configuration data storing parts; and 
 wherein the PLD configuration bits programming circuit is configured to automatically cause the global disabling circuit to assert the global output disable signal while new configuration data is being programmed into the selected subsets of the reprogrammable configuration data storing parts. 
 
     
     
       33. The PLD of  claim 32  wherein:
 wherein the PLD configuration bits programming circuit is configured to automatically cause the global disabling circuit to de-assert the global output disable signal when new configuration data is finished being programmed into the selected subsets of the reprogrammable configuration data storing parts and the corresponding configuration data outputting parts of the programmable configuration memory are then outputting the newly programmed data of the selected subsets of the reprogrammable configuration data storing parts. 
 
     
     
       34. The PLD of  claim 33  wherein the configuration bits programming circuit is configured to fetch the new configuration data that is to be sequentially supplied to selectable subsets of the reprogrammable configuration data storing parts of the PLD from a nonvolatile configuration data storing part also formed on the monolithically integrated circuit together with the PLD. 
     
     
       35. A machine-implemented and automated method of configuring a programmable logic device (PLD) that is formed as part of a monolithically integrated circuit, where the to-be-configured PLD has:
 a reconfigurable memory that can store supplied configuration data; 
 a first plurality of input selective first components each having a respective plurality of first input terminals and a respective input selecting capability whereby the first component can select a subset from among a set of input signals received by its respective plurality of first input terminals; 
 a second plurality of selection signal conveying lines that are operatively coupled to the reconfigurable memory so as to convey from the reconfigurable memory, corresponding first input selecting signals to corresponding ones of the input selective first components, where each of the first components is thereby configured to select its respective subset of input signals in accordance with the first input selecting signal conveyed thereto, where each of the first input selecting signals represents a respective plurality of bits that, when they are all used within the PLD, are capable of defining 2 n  unique states, where n is a whole number greater than 1; 
 a plurality of tristate drivers each having a tristateable output terminal, an output enabling terminal that can switch the tristateable output terminal into a high impedance (Hi-Z) mode, and a tristate driver input terminal; 
 a global selection establishing circuit that is structured to be selectively activated, and when activated, to cause all the first input selecting signals to represent a predetermined one among the 2 n  unique states; and 
 a global disabling circuit that is commandable to selectively output a global output disable signal which causes the outputs of all the tristate drivers of the PLD to be switched into their respective Hi-Z modes; 
 wherein each of the input selective first components has no more than 2 n −1 usable input terminals as its respective plurality of first input terminals, and 
 wherein each of the input selective first components automatically responds to the predetermined one of the 2 n  unique states being represented by its first input selecting signal, by switching into a no-usable-input-selected state wherein the input selective first component does not use any of the up to 2 n −1 input signals that may be present on its no more than 2 n −1 usable input terminals; 
 said automated method comprising:
 detecting a machine state that is predetermined to indicate a start of a reconfiguration operation for the PLD; 
 in response to said detecting, commanding the global disabling circuit to selectively output the global output disable signal which causes the outputs of all the tristate drivers of the PLD to be switched into their respective Hi-Z modes; 
 in response to said detecting, temporarily activating and then deactivating the global selection establishing circuit so as to thereby globally configure at least those parts of the reconfigurable memory that supply the first input selecting signals to states respectively representing the no-usable-input-selected state so as to thereby cause all the respective first input selecting signals to represent the no-usable-input-selected state; and 
 after said temporary activating and deactivating of the global selection establishing circuit, selectively altering the configuration states of one or more of the reconfigurable memory parts that supply the first input selecting signals to states other than those representing the no-usable-input-selected state. 
 
 
     
     
       36. The automated PLD configuring method of  claim 35  wherein:
 the no-usable-input-selected state is represented by digital data defining all its bits as logically zeroed bits; and 
 the global selection establishing circuit, when activated, resets at least the reconfigurable memory parts that supply the first input selecting signals to states representing digital data having all its corresponding bits reset to logical zero. 
 
     
     
       37. The automated PLD configuring method of  claim 35  wherein:
 a first machine state that is predetermined to indicate a start of a reconfiguration operation for the PLD is a power up state. 
 
     
     
       38. The automated PLD configuring method of  claim 35  and further comprising:
 determining if completion has been achieved at least for said selective altering of the configuration states of one or more of the reconfigurable memory parts that supply the first input selecting signals to states other than those representing the no-usable-input-selected state; and 
 in response to the determining of completion, commanding the global disabling circuit to discontinue its output of the global output disable signal. 
 
     
     
       39. A programmable logic device (PLD) comprising: at least one conductor; at least one tristate driver having an input terminal, an output enabling terminal, and an output terminal, the output terminal connected to the conductor; a multiplexer having a plurality of input terminals, at least one input selection terminal, and an output terminal, the output terminal connected to the input terminal of the tristate driver; and an output enabling circuit coupled to the output enabling terminal of the tristate driver and responsive to an input selecting signal applied to the input selection terminal of the multiplexer, wherein the output enabling circuit is structured to prevent the tristate driver from being in signal outputting state other than a high impedance (Hi-Z) output state when the input selecting signal selects none of the multiplexer input terminals. 
     
     
       40. The PLD of claim 39, wherein the output enabling circuit is structured to enable the tristate driver if the input selecting signal selects one of the multiplexer input terminals. 
     
     
       41. The PLD of claim 39, wherein the multiplexer has at least two input selection terminals and at least three input terminals. 
     
     
       42. The PLD of claim 39, wherein: the multiplexer has n input selection terminals and no more than 2n-1 input terminals; and n is a whole number greater than 1. 
     
     
       43. The PLD of claim 39, wherein the conductor is a longline. 
     
     
       44. The PLD of claim 43, wherein the longline extends across a plurality of substantially repeating tile structures of the PLD. 
     
     
       45. The PLD of claim 43, including a plurality of tristate drivers connected to the longline. 
     
     
       46. The PLD of claim 39, wherein the output enabling circuit comprises a logic OR circuit coupled between the output enabling terminal of the tristate driver and configuration memory bits for storing the input selecting signal applied to the input selection terminal of the multiplexer. 
     
     
       47. A method of configuring a programmable logic device (PLD) comprising: providing at least one conductor; providing at least one tristate driver having an output enabling terminal, an input terminal and an output terminal, the output terminal connected to the conductor; providing a multiplexer having a plurality of input terminals, at least one input selection terminal, and an output terminal, the output terminal connected to the input terminal of the tristate driver; providing an input selecting signal to the multiplexer input selection terminal; providing an output enabling circuit coupled to the output enabling terminal of the tristate driver, the circuit responsive to an input selecting signal from configuration memory bits for the input selection terminal of the multiplexer; and setting the configuration memory bits to a first logic state to generate an input selecting signal that selects none of the multiplexer input terminals, wherein the output enabling circuit in response to the input selecting signal disables the tristate driver to a high impedance (Hi-Z) output state in response to an input selecting signal that selects none of the multiplexer input terminals, disabling the tristate driver to a high impedance (Hi Z) output state. 
     
     
       48. The method of claim 47, wherein disabling the tristate driver to a high impedance (Hi-Z) output state includes maintaining the tristate driver in a high impedance (Hi-Z) output state. 
     
     
       49. The method of claim 47 including: setting the configuration memory bits to a second logic state to generate an input selecting signal that selects one of the multiplexer input terminals, wherein the output enabling circuit in response to the input selecting signal enables the tristate driver.