Error estimation and correction in a two-channel time-interleaved analog-to-digital converter

Abstract

A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are π/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones.

What is claimed is: 
     
       1. A two-channel, time-interleaved analog to digital converter (ADC) system comprising:
 a clock signal generator, for generating a clock signal at a frequency f and a period T; 
 a first ADC coupled to the clock signal generator, the first ADC sampling and holding an input signal on odd cycles of the clock signal to provide a first digital signal; 
 a second ADC coupled to the clock signal generator, the second ADC sampling and holding the input signal on even cycles of the clock signal to provide a second digital signal; 
 an error measurement block coupled to receive the first and second digital signals, the error measurement block producing an error signal based on the first and second digital signals; 
 an adaptive processor coupled to receive the error signal, the adaptive processor estimating at least one of offset, gain, and sample-time errors between the first and second ADCs based on the error signal, the adaptive processor feeding back a correction signal corresponding to the estimated error to correct one of offset, gain, and sample-time error of at least one of the first and second ADCs; and 
 a multiplexer, for interleaving the first and second digital signals to form a digital representation of the input signal. 
 
     
     
       2. The system of  claim 1  wherein the first ADC and second ADC are charge-domain pipelined ADCs, and the correction signal is fed back via an input stage of a charge-domain pipeline. 
     
     
       3. The system of  claim 1  wherein the adaptive processor estimates offset error by measuring an error signal based on an intereference tone that depends upon a difference in an amplitude offset between the first and second ADCs. 
     
     
       4. The system of  claim 1  wherein the adaptive processor estimates gain error by measuring an error signal based on a difference in power of the first and second digital signals. 
     
     
       5. The system of  claim 1  wherein the adaptive processor estimates sample-time error by determining a correlation between the first and second digital signals. 
     
     
       6. The system of  claim 1  wherein the adaptive processor sequentially processes offset, gain, and sample-time errors. 
     
     
       7. The system of  claim 6  further including plural look-up tables (LUTs) coupled to the adaptive processor, where the correction signal is based on addresses of the LUTs, and each LUT contains values used to control one of an offset setting, gain setting, or delay setting of at least one of the first and second ADCs. 
     
     
       8. The system of  claim 6  further including plural digital-to-analog converters (DACs), where the correction signal is provided to the DACs, and each DAC controls one of an offset setting, gain setting, or delay setting of at least one of the first and second ADCs. 
     
     
       9. The system of  claim 1 , further including additional adaptive processors, the adaptive processors configured to process offset, gain, and sample-time errors in parallel. 
     
     
       10. The system of  claim 1  wherein the adaptive processor includes:
 a signum block for determining a sign of the error signal; 
 a multiplier for multiplying the sign of the error signal with an address step size; 
 a feedback loop for summing and delaying an output of the multiplier; and 
 a rounding block for rounding an output of the feedback loop. 
 
     
     
       11. The system of  claim 10  wherein the error measurement block includes:
 a subtractor for taking a difference of the first and second digital signals; and 
 a feedback loop for summing and delaying an output of the subtractor to provide the error signal. 
 
     
     
       12. The system of  claim 10  wherein the error measurement block includes:
 a first multiplier for squaring the first digital signal; 
 a second multiplier for squaring the second digital signal; 
 a subtractor for taking the difference of outputs from the first and second multipliers; and 
 a feedback loop for summing and delaying an output of the subtractor to provide the error signal. 
 
     
     
       13. The system of  claim 10  wherein the error measurement block includes:
 a first subtractor for taking a difference of the first and second digital signals; 
 a delay element for delaying the first digital signal; 
 a second subtractor for taking a difference of the second digital signal and an output from the delay element; 
 a first multiplier for squaring an output from the first subtractor; 
 a second multiplier for squaring an output from the second subtractor; 
 a third subtractor for taking a difference of outputs from the first and second multipliers; and 
 a feedback loop for summing and delaying an output of the third subtractor to provide the error signal. 
 
     
     
       14. The system of  claim 1  wherein the adaptive processor estimates and corrects errors using hardware. 
     
     
       15. The system of  claim 1  wherein the adaptive processor estimates and corrects errors using software. 
     
     
       16. The system of  claim 1  further including plural look-up tables (LUTs), each LUT coupled to the adaptive processor and configured to provide the correction signal to the second ADC for one of offset, gain, or sample-time error based on output from the adaptive processor. 
     
     
       17. A method for correcting errors in a two-channel, time-interleaved analog to digital converter (ADC) comprising:
 generating a clock signal at a frequency f and a period T with a clock signal generator; 
 sampling and holding an input signal with first and second ADCs at alternating sample time intervals 2T to produce first and second digital signals, respectively; 
 determining an error signal based on the first and second digital signals with an error measurement block; 
 estimating at least one of offset, gain, and sample-time error between the first and second ADCs based on the error signal with an adaptive processor; 
 providing a correction signal based on the error estimated by the adaptive processor; 
 applying the correction signal to at least one of the first and second ADCs to correct one of offset, gain, and sample-time error; and 
 interleaving the first and second digital signals with a multiplexer to form a digital representation of the input signal. 
 
     
     
       18. The method of  claim 17  wherein the first and second ADCs are charge-domain pipelined ADCs and the correction signal is applied to an input stage of a charge-domain pipeline. 
     
     
       19. The method of  claim 17  wherein estimating offset error includes measuring an error signal based on an intereference tone whose amplitude depends upon a difference in amplitude offset between the first and second ADCs. 
     
     
       20. The method of  claim 17  wherein estimating gain error includes measuring an error signal based on a difference in power of the first and second digital signals. 
     
     
       21. The method of  claim 17  wherein estimating sample-time error includes determining a correlation between the first and second digital signals. 
     
     
       22. The method of  claim 17  wherein offset, gain, and sample-time errors are sequentially estimated and corrected. 
     
     
       23. The method of  claim 22  wherein providing the correction signal includes looking up address values corresponding to offset, gain, or sample-time errors in a look-up table. 
     
     
       24. The method of  claim 22  wherein providing the correction signal includes converting digital values corresponding to offset, gain, and sample-time errors to corresponding analog offset, gain, and sample-time settings. 
     
     
       25. The method of  claim 17 , wherein offset, gain, and sample-time errors are estimated in parallel. 
     
     
       26. The method of  claim 17  wherein estimating errors includes:
 determining a sign of the error signal with a signum block; 
 multiplying the sign of the error signal with an address step size with a multiplier; 
 summing and delaying an output of the multiplier with a feedback loop; and 
 rounding an output of the feedback loop with a rounding block. 
 
     
     
       27. The method of  claim 26  wherein determining the error signal further includes:
 taking a difference of the first and second digital signals with a subtractor; and 
 summing and delaying an output of the subtractor with a feedback loop to provide the error signal. 
 
     
     
       28. The method of  claim 26  wherein determining the error signal further includes:
 squaring the first digital signal with a first multiplier; 
 squaring the second digital signal with a second multiplier; 
 taking a difference of outputs from the first and second multipliers with a subtractor; and 
 summing and delaying an output of the subtractor with a feedback loop to provide the error signal. 
 
     
     
       29. The method of  claim 26  wherein determining the error signal further includes:
 taking a difference of the first and second digital signals with a first subtractor; 
 delaying the first digital signal with a delay element; 
 taking a difference of the second digital signal and an output from the delay element; 
 squaring an output from the first subtractor with a first multiplier; 
 squaring an output from the second subtractor with a second multiplier; 
 taking a difference of outputs from the first and second multipliers with a third subtractor; and 
 summing and delaying an output of the third subtractor with a feedback loop to provide the error signal. 
 
     
     
       30. The method of  claim 17  wherein the adaptive processor estimates errors using hardware. 
     
     
       31. The method of  claim 17  wherein the adaptive processor estimates errors using software. 
     
     
       32. The method of  claim 17  wherein providing the correction signal includes setting an offset, gain, or sample-time setting on the second ADC according to address values corresponding offset, gain, or sample-time errors, respectively, stored on corresponding look-up tables. 
     
     
       33. A two-channel, time-interleaved analog to digital converter (ADC) comprising:
 a clock signal generator for generating a clock signal; 
 a first ADC for receiving the clock signal and sampling and holding an input on odd cycles of the clock signal; 
 a second ADC for receiving the clock signal and sampling and holding the input on even cycles of the clock signal; 
 error signal blocks for receiving outputs of the first and second ADCs and providing error signals corresponding to offset, gain, and phase errors of the outputs; 
 look-up tables (LUTs) for storing values used to control one of an offset setting, gain setting, or delay setting of at least one of the first and second ADCs; and 
 an adaptive processor for receiving the error signals and sequentially estimating the offset, gain, and phase error based on the error signals, the adaptive processor further sequentially providing corresponding corrections of the offset, gain, and phase errors based on the values stored in the LUTs to the first and second ADCs. 
 
     
     
       34. A time-interleaved analog to digital converter (ADC) apparatus comprising:
 a first ADC, to sample and hold an input signal to provide a first digital signal;   a second ADC, to sample and hold the input signal to provide a second digital signal;   an error signal estimator coupled to receive the first and second digital signal and to provide at least one digital error signal corresponding to offset, gain, and/or sample-time errors of the first and second ADCs; and   a converter, to convert the at least one digital error signal to a corresponding analog correction signal and to couple the analog correction signal to control one of an offset setting, gain setting, or delay setting of at least one of the first and second ADCs; and   a multiplexer, to interleave the first and second digital signals to form a digital representation of the input signal.   
     
     
       35. The apparatus of claim 34 wherein the first ADC and second ADC are charge-domain pipelined ADCs, and the analog correction signal is fed to control an input stage of at least one of the charge-domain pipeline. 
     
     
       36. The apparatus of claim 34 wherein the estimator estimates offset error by measuring an error signal based on an intereference tone that depends upon a difference in an amplitude offset between the first and second ADCs. 
     
     
       37. The apparatus of claim 34 wherein the estimator estimates gain error by measuring an error signal based on a difference in power of the first and second digital signals. 
     
     
       38. The apparatus of claim 34 wherein the estimator estimates sample-time error by determining a correlation between the first and second digital signals. 
     
     
       39. The apparatus of claim 34 wherein the estimator sequentially processes offset, gain, and sample-time errors. 
     
     
       40. The apparatus of claim 34 further including plural look-up tables (LUTs) coupled to the estimator, where the correction signal is based on addresses of the LUTs, and each LUT contains values used to control one of an offset setting, gain setting, or delay setting of at least one of the first and second ADCs. 
     
     
       41. The apparatus of claim 34 further including plural digital-to-analog converters (DACs), where the correction signal is provided to the DACs, and each DAC controls one of an offset setting, gain setting, or delay setting of at least one of the first and second ADCs. 
     
     
       42. The apparatus of claim 34, further including additional estimators configured to process offset, gain, and sample-time errors in parallel. 
     
     
       43. The apparatus of claim 34 wherein the estimator includes:
 a signum block for determining a sign of the digital error signal;   a multiplier for multiplying the sign of the digital error signal with an error step size;   a feedback loop for summing and delaying an output of the multiplier; and   a rounding block for rounding an output of the feedback loop.   
     
     
       44. The apparatus of claim 43 wherein the estimator includes:
 a subtractor for taking a difference of the first and second digital signals; and   a feedback loop for summing and delaying an output of the subtractor to provide the digital error signal.   
     
     
       45. The apparatus of claim 43 wherein the estimator includes:
 a first multiplier for squaring the first digital signal;   a second multiplier for squaring the second digital signal;   a subtractor for taking the difference of outputs from the first and second multipliers; and   a feedback loop for summing and delaying an output of the subtractor to provide the digital error signal.   
     
     
       46. The apparatus of claim 43 wherein the estimator includes:
 a first subtractor for taking a difference of the first and second digital signals;   a delay element for delaying the first digital signal;   a second subtractor for taking a difference of the second digital signal and an output from the delay element;   a first multiplier for squaring an output from the first subtractor;   a second multiplier for squaring an output from the second subtractor;   a third subtractor for taking a difference of outputs from the first and second multipliers; and   a feedback loop for summing and delaying an output of the third subtractor to provide the digital error signal.   
     
     
       47. The apparatus of claim 34 further including plural look-up tables (LUTs), each LUT coupled to the error signal estimator and configured to provide the correction signal to the second ADC for one of offset, gain, or sample-time error based on output from the adaptive processor. 
     
     
       48. A method comprising:
 a first step of analog to digital converting an input signal to provide a first digital signal;   a second step of analog to digital converting the input signal to provide a second digital signal;   estimating, from the first and second digital signal, at least one digital error signal corresponding to offset, gain, and/or phase errors of at least one of the first and/or second steps of analog to digital converting, to produce a digital error signal;   coupling the at least one digital error signal to control one of an offset setting, gain setting, or delay setting of at least one of the first and second analog to digital converting steps; and   multiplexing the first and second digital signal to form a digital representation of the input signal.   
     
     
       49. The method of claim 48 wherein the first step and second step of analog to digital converting are charge-domain pipelined and the digital error signal is coupled to control an input stage of at least one of the charge domain pipelines of a charge-domain pipeline. 
     
     
       50. The method of claim 48 wherein the estimator further measures an error signal based on an intereference tone that depends upon a difference in an amplitude offset between the first and second analog to digital converting steps. 
     
     
       51. The method of claim 48 wherein the estimating estimates gain error by measuring an error signal based on a difference in power of the first and second digital signals. 
     
     
       52. The method of claim 48 wherein the estimating estimates sample-time error by determining a correlation between the first and second digital signals. 
     
     
       53. The method of claim 48 wherein the estimating sequentially processes offset, gain, and sample-time errors. 
     
     
       54. The method of claim 48 further comprising:
 one or more digital-to-analog converting steps, where the digital correction signal is converted to an analog signal to control one of an offset setting, gain setting, or delay setting of at least one of the first and/or second analog to digital converting steps.   
     
     
       55. The method of claim 48, further comprising estimating offset, gain, and sample-time errors in parallel with one another. 
     
     
       56. The method of claim 48 wherein estimating includes:
 determining a sign of the error signal;   multiplying the sign of the error signal with an offset step size; and   summing and delaying an output of the multiplying step.   
     
     
       57. The method of claim 48 wherein the estimating includes:
 taking a difference of the first and second digital signals; and   summing and delaying the difference to provide the error signal.   
     
     
       58. The method of claim 48 wherein the estimating includes:
 squaring the first digital signal;   squaring the second digital signal;   taking a difference of outputs from the first and second squaring steps; and   summing and delaying the difference to provide the error signal.   
     
     
       59. The method of claim 48 further comprising:
 taking a first difference of the first and second digital signals;   delaying the first digital signal;   taking a second difference of the second digital signal and the delayed first digital signal;   squaring the first difference;   squaring the second difference; and   taking a third difference of the results of first and second squaring steps.   
     
     
       60. An apparatus comprising:
 a first analog to digital converter for converting an input signal to provide a first digital signal;   a second analog to digital converter for converting the input signal to provide a second digital signal;   a programmable processor containing executable code for:
 estimating, from the first and second digital signal, at least one digital error signal corresponding to offset, gain, and/or phase errors of at least one of the first and/or second steps of analog to digital converting, to produce a digital error signal; and 
 controlling at least one of an offset setting, gain setting, or delay setting of at least one of the first and second analog to digital converters; and 
   a multiplexer, for interleaving the first and second digital signals to provide a digital representation of the input signal.