System and method for encoding data transmitted on a bus

Abstract

An apparatus having a corresponding method comprises a transmit circuit to transmit data, the transmit circuit comprising a transmit input circuit to input the data, and an address for the data, to the transmit circuit, an encoder to encode the data according to the address for the data, comprising an encode select circuit to select one of a plurality of keys based on the address for the data, and an encoding circuit to encode the data using the key selected by the encode select circuit, and a transmit output circuit to output the encoded data.

What is claimed is: 
     
       1. An apparatus comprising:
 a transmit circuit to transmit data from a first device to a second device on a bus, the bus connecting the first device and the second device, the transmit circuit comprising:
 a transmit input circuit to input the data and an address for the data to the transmit circuit, 
 an encoder to encode the data according to the address for the data, the encoder comprising:
 an encode select circuit to (i) select one of a plurality of keys based on the address for the data and (ii) hash at least a portion of the address to obtain an index to a table containing the plurality of keys, wherein different keys are selected for different addresses when transmitting data from the first device to the second device, and 
 an encoding circuit to encode the data using the key selected by the encode select circuit, and 
 
 a transmit output circuit to output the encoded data on the bus. 
   
     
     
       2. The apparatus of  claim 1 , further comprising:
 a receive circuit to receive the encoded data from the bus, the receive circuit comprising:
 a receive input circuit to input the encoded data and an address for the encoded data to the receive circuit, 
 a decoder to decode the encoded data according to the address for the encoded data, the decoder comprising:
 a decode select circuit to select a second one of the plurality of keys based on the address for the encoded data, and 
 a decoding circuit to decode the encoded data using the second one of the plurality of keys selected by the decode select circuit, and 
 
 a receive output circuit to output the decoded data. 
   
     
     
       3. The apparatus of  claim 1 :
 wherein the encoding circuit comprises   a plurality of exclusive-or (XOR) gates each comprising
 a first input to input a respective bit of the data, 
 a second input to input a respective bit of the key selected by the encode select circuit, and 
 an output to output a respective bit of the encoded data. 
   
     
     
       4. The apparatus of  claim 2 :
 wherein the decoding circuit comprises   a plurality of exclusive-or (XOR) gates each comprising
 a first input to input a respective bit of the encoded data, 
 a second input to input a respective bit of the second one of the plurality of keys selected by the decode select circuit, and 
 an output to output a respective bit of the data. 
   
     
     
       5. The apparatus of  claim 2 , further comprising:
 a memory;   wherein the encoder further comprises a random number generator to generate random numbers;   wherein the encode select circuit selects the one of the plurality of keys according to one of the random numbers; and   wherein the memory stores an association between the address for the data and the one of the random numbers.   
     
     
       6. The apparatus of  claim 5 :
 wherein the decode select circuit retrieves from the memory a second association between the address for the encoded data and a second one of the random numbers based on the address for the encoded data; and   wherein the decode select circuit selects the second one of the plurality of keys according to the second one of the random numbers.   
     
     
       7. The apparatus of  claim 2 , further comprising:
 a memory;   wherein the address for the data, and the address for the encoded data, comprise at least one of the group consisting of
 an address in the memory, and 
 a buffer number in the memory. 
   
     
     
       8. An integrated circuit comprising the apparatus of  claim 1 . 
     
     
       9. A method comprising:
 transmitting (i) data and (ii) an address for the data from a first device to a second device on a bus, the bus connecting the first device and the second device;   encoding the data according to the address for the data by:
 selecting one of a plurality of keys based on the address for the data; 
 hashing at least a portion of the address to obtain an index to a table containing the plurality of keys, wherein different keys are selected for different addresses when transmitting data from the first device to the second device; and 
 encoding the data using the key selected based on the address for the data; and 
 outputting the encoded data on the bus. 
   
     
     
       10. The method of  claim 9 , further comprising:
 decoding the encoded data according to the address for the encoded data by:
 selecting a second one of the plurality of keys based on the address for the encoded data; and 
 decoding the encoded data using the second one of the plurality of keys selected based on the address for the encoded data. 
   
     
     
       11. The method of  claim 9 :
 wherein encoding the data using the key selected based on the address for the data comprises generating a bitwise exclusive-or (XOR) of the data and the key selected based on the address for the data.   
     
     
       12. The method of  claim 10 :
 wherein decoding the encoded data using the second one of the plurality of keys selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the second one of the plurality of keys selected based on the address for the encoded data.   
     
     
       13. An apparatus comprising:
 a receive circuit to receive data that is encoded from a bus, the receive circuit comprising:
 a receive input circuit to input the encoded data and an address for the encoded data received from the bus to the receive circuit, 
 a decoder to decode the encoded data according to the address for the encoded data, the decoder comprising:
 a decode select circuit to select one of the plurality of keys based on the address for the encoded data, and 
 a decoding circuit to decode the encoded data using the key selected by the decode select circuit, and 
 
 a receive output circuit to output the decoded data. 
   
     
     
       14. The apparatus of  claim 13 :
 wherein the decoding circuit comprises   a plurality of exclusive-or (XOR) gates each comprising
 a first input to input a respective bit of the encoded data, 
 a second input to input a respective bit of the key selected by the decode select circuit, and 
 an output to output a respective bit of the data. 
   
     
     
       15. The apparatus of  claim 13 , further comprising:
 a memory;   wherein the address of the encoded data comprises at least one of the group consisting of
 an address in the memory, and 
 a buffer number in the memory. 
   
     
     
       16. An integrated circuit comprising the apparatus of  claim 13 . 
     
     
       17. A method comprising:
 inputting encoded data and an address for the encoded data received from a bus;   decoding the encoded data according to the address for the encoded data; and   outputting the decoded data.   
     
     
       18. The method of  claim 17 :
 wherein decoding comprises
 selecting one of a plurality of keys based on the address for the encoded data, and 
 decoding the encoded data using the key selected based on the address for the encoded data. 
   
     
     
       19. The method of  claim 18 :
 wherein decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.   
     
     
       20. A method of reducing an amount of simultaneously switched outputs of a memory device, comprising:
 driving outputs of the memory device to a set of values;   randomly encoding the set of values based on a random number to reduce an amount of simultaneously switched outputs resulting from switching of the set of values to another set of values; and   driving the outputs of the memory device to the randomly encoded set of values.    
     
     
       21. The method according to claim 20, further comprising:
 decoding the randomly encoded set of values back to the set of values.    
     
     
       22. An interface of a device that is coupled to a memory, comprising:
 an output driving circuit that is coupled to outputs of the device, the output driving circuit being configured to drive the outputs of the device to a set of values;   a random number generator configured to generate a random number; and   an encoder that is coupled to the output driving circuit, the encoder being configured to receive the set of values and to randomly encode the set of values based on the random number to reduce an amount of simultaneously switched outputs resulting from switching of the set of values to another set of values,   wherein the output driving circuit drives the outputs of the device to the randomly encoded set of values.    
     
     
       23. The interface according to claim 22, wherein the memory comprises:
 a decoder configured to decode the randomly encoded set of values back to the set of values.    
     
     
       24. A semiconductor device having reduced simultaneously switched outputs, comprising:
 an output driving circuit that is coupled to outputs of the semiconductor device, the output driving circuit being configured to drive the outputs to a set of values;   a random number generator configured to generate a random number; and   an encoder that is coupled between the semiconductor device and the output driving circuit, the encoder being configured to receive the set of values from the output driving circuit and to randomly encode the set of values based on the random number to reduce an amount of simultaneously switched outputs resulting from switching of the set of values to another set of values.    
     
     
       25. The semiconductor device according to claim 24, wherein the outputs of the semiconductor device are coupled to a memory to store the set of values, the memory comprises:
 a decoder configured to decode the randomly encoded set of values back to the set of values.