Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

The invention claimed is: 
     
       1. A nonvolatile semiconductor memory device comprising:
 a memory cell having a variable resistive element having two terminals, the variable resistive element having resistive characteristics defined by current-voltage characteristics at both ends, the resistive characteristics transiting between two stably provided resistive characteristics of a low resistance state and a high resistance state when a voltage satisfying a predetermined condition is applied to the both ends; 
 a load circuit connected to one end of the variable resistive element in series, the load circuit having load resistive characteristics defined by the current-voltage characteristics, the load resistive characteristics being switched between first load resistive characteristics and second load resistive characteristics, the second load resistive characteristics having a resistance higher than the first load resistive characteristics; and 
 a voltage generation circuit for applying a voltage to both ends of a serial circuit configured by the variable resistive element and the load circuit, wherein 
 a stored state of the variable resistive element is determined whether the resistive characteristics are in the low resistance state or the high resistance state and written when the resistive characteristics transit between the low resistance state and the high resistance state in response to application of a voltage to the both ends of the variable resistive element, 
 the variable resistive element shows asymmetric characteristics in which when a polarity of an applied voltage to one terminal based on the other terminal is a first polarity, a first threshold voltage is lower than a second threshold voltage, the first threshold voltage being a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the low resistance state to the high resistance state, the second threshold voltage being a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the high resistance state to the low resistance state, and when the polarity of the applied voltage is a second polarity different from the first polarity, the first threshold voltage is higher than the second threshold voltage, 
 the load resistive characteristics of the load circuit are switched so as to show the first load resistive characteristics during a first writing operation in which the resistive characteristics of the variable resistive element transit from the low resistance state to the high resistance state, and show the second load resistive characteristics during a second writing operation in which the resistive characteristics of the variable resistive element transit from the high resistance state to the low resistance state, and 
 the voltage generation circuit applies a first writing voltage to the both ends of the serial circuit of the variable resistive element and the load circuit so that a voltage of the first polarity having an absolute value equal to or higher than the first threshold voltage is applied to the both ends of the variable resistive element of the memory cell to be written during the first writing operation, and applies a second writing voltage to the both ends of the serial circuit of the variable resistive element and the load circuit so that the voltage of the first polarity having the absolute value equal to or higher than the second threshold voltage is applied to the both ends of the variable resistive element of the memory cell to be written during the second writing operation. 
 
     
     
       2. The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the variable resistive element has a three-layer structure in which a variable resistor is sandwiched between a first electrode and a second electrode. 
 
     
     
       3. The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the memory cell has a rectifying element connected to the variable resistive element in series, and 
 the rectifying element provides forward bias when the voltage having the first polarity is applied to the both ends of the variable resistive element. 
 
     
     
       4. The nonvolatile semiconductor memory device according to  claim 3 , wherein
 when the first polarity is a positive polarity, a Schottky barrier diode is provided at an interface between an N-type polycrystalline semiconductor and a lower electrode that is the lower of the first electrode and the second electrode, the N-type polycrystalline semiconductor being formed so as to be in contact with a lower surface of the lower electrode, and 
 when the first polarity is a negative polarity, the Schottky barrier diode is provided at an interface between a P-type polycrystalline semiconductor and the lower electrode, the P-type polycrystalline semiconductor being formed so as to be in contact with the lower surface of the lower electrode. 
 
     
     
       5. The nonvolatile semiconductor memory device according to  claim 4 , wherein
 when the first polarity is the positive polarity, a P-type impurity is implanted to a part of a contact region with the lower electrode in the N-type polycrystalline semiconductor, and 
 when the first polarity is the negative polarity, an N-type impurity is implanted to a part of the contact region with the lower electrode in the P-type polycrystalline semiconductor. 
 
     
     
       6. The nonvolatile semiconductor memory device according to  claim 3 , wherein
 when the first polarity is a positive polarity, a PN junction diode includes a P-type upper polycrystalline semiconductor formed so as to be in contact with a lower layer of the lower electrode, and an N-type lower polycrystalline semiconductor formed so as to be in contact with a lower layer of the upper polycrystalline semiconductor, and 
 when the first polarity is a negative polarity, a PN junction diode includes an N-type upper polycrystalline semiconductor formed so as to be in contact with a lower layer of the lower electrode, and a P-type lower polycrystalline semiconductor formed so as to be in contact with a lower layer of the upper polycrystalline semiconductor. 
 
     
     
       7. A device comprising:
 a memory cell including a variable resistive element having two terminals;   a load circuit connected to the variable resistive element and configured to switch load resistive characteristics between first load resistive characteristics and second load resistive characteristics, wherein the second load resistive characteristics have a resistance higher than the first load resistive characteristics; and   a voltage generation circuit configured to apply a voltage to a circuit formed by the variable resistive element and the load circuit;   wherein the variable resistive element is configured to write to a stored state upon changing between a low resistance state and a high resistance state in response to application of the voltage to the variable resistive element;   wherein the variable resistive element is configured to show asymmetric characteristics such that, when a polarity of an applied voltage to a first terminal of the memory cell compared to a second terminal is a first polarity, a first threshold voltage is lower than a second threshold voltage, wherein the first threshold voltage comprises a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the low resistance state to the high resistance state, and wherein the second threshold voltage comprises a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the high resistance state to the low resistance state; and   wherein the load circuit is further configured to switch the load resistive characteristics to show:
 the first load resistive characteristics during a first writing operation in which the load resistive characteristics of the variable resistive element transit from the low resistance state to the high resistance state; and 
 the second load resistive characteristics during a second writing operation in which the load resistive characteristics of the variable resistive element transit from the high resistance state to the low resistance state.  
   
     
     
       8. The device of claim 7, wherein the voltage generation circuit is further configured to:
 apply a first writing voltage to the circuit formed by the variable resistive element and the load circuit so that a voltage of the first polarity having an absolute value equal to or higher than the first threshold voltage is applied to the variable resistive element during the first writing operation; and   apply a second writing voltage to the circuit formed by the variable resistive element and the load circuit so that the voltage of the first polarity having the absolute value equal to or higher than the second threshold voltage is applied to the variable resistive element during the second writing operation.    
     
     
       9. The device of claim 7, wherein the variable resistive element has a three-layer structure, and wherein the three-layer structure comprises a first electrode, a second electrode, and a variable resistor positioned between the first electrode and the second electrode.  
     
     
       10. The device of claim 9, further comprising a Schottky barrier diode located at an interface between an N-type polycrystalline semiconductor and a lower electrode that is the lower of the first electrode and the second electrode, wherein the N-type polycrystalline semiconductor is in contact with a lower surface of the lower electrode.  
     
     
       11. The device of claim 10, wherein the lower electrode comprises a contact region including an implanted P-type impurity.  
     
     
       12. The device of claim 10, further comprising a PN junction diode including:
 a P-type upper polycrystalline semiconductor in contact with a lower layer of the lower electrode; and   an N-type lower polycrystalline semiconductor in contact with a lower layer of the P-type upper polycrystalline semiconductor.    
     
     
       13. The device of claim 9, further comprising a Schottky barrier diode located at an interface between a P-type polycrystalline semiconductor and a lower electrode that is the lower of the first electrode and the second electrode, wherein the P-type polycrystalline semiconductor is in contact with a lower surface of the second electrode.  
     
     
       14. The device of claim 13, wherein the lower electrode comprises a contact region including an implanted N-type impurity.  
     
     
       15. The device of claim 13, further comprising a PN junction diode including:
 an N-type upper polycrystalline semiconductor in contact with a lower layer of the lower electrode; and   a P-type lower polycrystalline semiconductor in contact with a lower layer of the N-type upper polycrystalline semiconductor.    
     
     
       16. The device of claim 7, wherein the memory cell comprises a rectifying element connected to the variable resistive element in series, and wherein the rectifying element is configured to provide a forward bias when the applied voltage having the first polarity is applied to the variable resistive element.  
     
     
       17. The device of claim 7, further comprising a word line selection circuit configured to:
 select a word line of a memory cell array that corresponds to an address signal; and   apply a selected word line voltage to the selected word line for respective memory operations.    
     
     
       18. The device of claim 7, further comprising a bit line selection circuit configured to:
 select a bit line of a memory cell array that corresponds to an address signal; and   individually apply a selected bit line voltage to the selected bit line for respective memory operations.    
     
     
       19. The device of claim 7, further comprising a voltage switching circuit configured to:
 apply a selected word line voltage and an unselected word line voltage to a word line selection circuit; and   apply a selected bit line voltage and an unselected bit line voltage to a bit line selection circuit.